Searched refs:opc2 (Results 1 - 3 of 3) sorted by relevance
| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_emit_gk110.cpp | 46 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
423 CodeEmitterGK110::emitForm_21(const Instruction *i, uint32_t opc2, in emitForm_21() argument
437 code[1] = (0xc << 28) | (opc2 << 20); in emitForm_21()
1855 uint64_t opc1, opc2; in emitSUCalc() local
1864 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break; in emitSUCalc()
1865 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break; in emitSUCalc()
1866 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break; in emitSUCalc()
1871 emitForm_21(i, opc2, opc1); in emitSUCalc()
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| /third_party/node/deps/v8/src/execution/arm/ |
| H A D | simulator-arm.cc | 3544 int opc2 = instr->Bits(7, 5); in DecodeTypeCP15() local
3548 if (((crm == 10) && (opc2 == 5)) || // CP15DMB in DecodeTypeCP15()
3549 ((crm == 10) && (opc2 == 4)) || // CP15DSB in DecodeTypeCP15()
3550 ((crm == 5) && (opc2 == 4))) { // CP15ISB in DecodeTypeCP15()
4400 int opc2 = instr->Bits(10, 7); in DecodeAdvancedSIMDTwoOrThreeRegisters() local
4403 if (opc1 == 0 && (opc2 >> 2) == 0) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4485 } else if (opc1 == 0 && (opc2 == 0b0100 || opc2 == 0b0101)) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4507 } else if (opc1 == 0 && (opc2 == 0b1100 || opc2 in DecodeAdvancedSIMDTwoOrThreeRegisters()
[all...] |
| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.cc | 2327 // CP15DMB: CRn=c7, opc1=0, CRm=c10, opc2=5, Rt is ignored. in dmb()
2338 // CP15DSB: CRn=c7, opc1=0, CRm=c10, opc2=4, Rt is ignored. in dsb()
2349 // CP15ISB: CRn=c7, opc1=0, CRm=c5, opc2=4, Rt is ignored. in isb()
3025 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 1(19) | opc2(18-16) | in EncodeVCVT()
3029 int sz, opc2, op; in EncodeVCVT() local
3032 opc2 = IsSignedVFPType(dst_type) ? 0x5 : 0x4; in EncodeVCVT()
3037 opc2 = 0x0; in EncodeVCVT()
3042 return (cond | 0xE * B24 | B23 | D * B22 | 0x3 * B20 | B19 | opc2 * B16 | in EncodeVCVT()
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