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Searched refs:num_regs (Results 1 - 25 of 31) sorted by relevance

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/third_party/libunwind/libunwind/include/tdep-ia64/
H A Drse.h58 rse_skip_regs (uint64_t addr, long num_regs) in rse_skip_regs() argument
60 long delta = rse_slot_num(addr) + num_regs; in rse_skip_regs()
62 if (num_regs < 0) in rse_skip_regs()
64 return addr + ((num_regs + delta/0x3f) << 3); in rse_skip_regs()
/third_party/libunwind/libunwind/src/ia64/
H A DGstep.c70 unw_word_t sc_addr, num_regs; in linux_interrupt()
76 num_regs = c->cfm & 0x7f; in linux_interrupt()
78 num_regs = 0; in linux_interrupt()
87 *num_regsp = num_regs; /* size of frame */ in linux_interrupt()
224 unw_word_t prev_ip, prev_sp, prev_bsp, ip, num_regs; in update_frame_state() local
265 num_regs = 0; in update_frame_state()
274 if ((ret = linux_sigtramp (c, prev_cfm_loc, &num_regs)) < 0) in update_frame_state()
281 if ((ret = linux_interrupt (c, prev_cfm_loc, &num_regs, in update_frame_state()
288 if ((ret = hpux_sigtramp (c, prev_cfm_loc, &num_regs)) < 0) in update_frame_state()
311 num_regs in update_frame_state()
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H A DGscript.c372 int r, i, j, max, max_reg, max_when, num_regs = 0; in sort_regs() local
382 regorder[num_regs++] = r; in sort_regs()
389 for (i = max = 0; i < num_regs - 1; ++i) in sort_regs()
394 for (j = i + 1; j < num_regs; ++j) in sort_regs()
407 return num_regs; in sort_regs()
416 int num_regs, i, ret, regorder[IA64_NUM_PREGS - 3]; in build_script() local
467 num_regs = sort_regs (&sr, regorder); in build_script()
468 for (i = 0; i < num_regs; ++i) in build_script()
/third_party/mesa3d/src/gallium/auxiliary/util/
H A Du_simple_shaders.c1095 unsigned num_regs; in util_make_tess_ctrl_passthrough_shader() local
1110 num_regs = 0; in util_make_tess_ctrl_passthrough_shader()
1127 dst[num_regs] = ureg_DECL_output(ureg, in util_make_tess_ctrl_passthrough_shader()
1130 src[num_regs] = ureg_DECL_input(ureg, vs_semantic_names[j], in util_make_tess_ctrl_passthrough_shader()
1136 src[num_regs] = ureg_src_dimension(src[num_regs], 0); in util_make_tess_ctrl_passthrough_shader()
1137 dst[num_regs] = ureg_dst_dimension(dst[num_regs], 0); in util_make_tess_ctrl_passthrough_shader()
1140 num_regs++; in util_make_tess_ctrl_passthrough_shader()
1150 dst[num_regs] in util_make_tess_ctrl_passthrough_shader()
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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs.cpp1613 unsigned num_regs = MIN2(uniform_push_length - i, 4);
1614 assert(num_regs > 0);
1615 num_regs = 1 << util_logbase2(num_regs);
1635 fs_reg dest = retype(brw_vec8_grf(payload.num_regs + i, 0),
1641 unsigned send_width = MIN2(16, num_regs * 8);
1648 BRW_DATAPORT_OWORD_BLOCK_OWORDS(num_regs * 2));
1651 send->size_written = num_regs * REG_SIZE;
1654 i += num_regs;
1684 struct brw_reg brw_reg = brw_vec1_grf(payload.num_regs
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H A Dbrw_eu_emit.c588 unsigned num_regs, in gfx7_set_dp_scratch_message()
595 assert(num_regs == 1 || num_regs == 2 || num_regs == 4 || in gfx7_set_dp_scratch_message()
596 (devinfo->ver >= 8 && num_regs == 8)); in gfx7_set_dp_scratch_message()
597 const unsigned block_size = (devinfo->ver >= 8 ? util_logbase2(num_regs) : in gfx7_set_dp_scratch_message()
598 num_regs - 1); in gfx7_set_dp_scratch_message()
2162 int num_regs, in brw_oword_block_write_scratch()
2178 const unsigned mlen = 1 + num_regs; in brw_oword_block_write_scratch()
2257 BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_regs * in brw_oword_block_write_scratch()
583 gfx7_set_dp_scratch_message(struct brw_codegen *p, brw_inst *inst, bool write, bool dword, bool invalidate_after_read, unsigned num_regs, unsigned addr_offset, unsigned mlen, unsigned rlen, bool header_present) gfx7_set_dp_scratch_message() argument
2160 brw_oword_block_write_scratch(struct brw_codegen *p, struct brw_reg mrf, int num_regs, unsigned offset) brw_oword_block_write_scratch() argument
2271 brw_oword_block_read_scratch(struct brw_codegen *p, struct brw_reg dest, struct brw_reg mrf, int num_regs, unsigned offset) brw_oword_block_read_scratch() argument
2346 gfx7_block_read_scratch(struct brw_codegen *p, struct brw_reg dest, int num_regs, unsigned offset) gfx7_block_read_scratch() argument
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H A Dbrw_wm_iz.cpp168 payload.num_regs = reg; in setup_fs_payload_gfx4()
H A Dbrw_mesh.cpp1039 const unsigned num_regs = comp_offset + comps; in emit_urb_direct_reads() local
1042 fs_reg data = ubld8.vgrf(BRW_REGISTER_TYPE_UD, num_regs); in emit_urb_direct_reads()
1051 inst->size_written = num_regs * REG_SIZE; in emit_urb_direct_reads()
1219 assert(payload.num_regs == 3 || payload.num_regs == 4); in nir_emit_task_mesh_intrinsic()
1221 bld.MOV(dest, retype(brw_vec1_grf(payload.num_regs - 1, in nir_emit_task_mesh_intrinsic()
H A Dbrw_vec4.cpp1702 const unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE); in fixup_3src_null_dest() local
1704 inst->dst = retype(dst_reg(VGRF, alloc.allocate(num_regs)), in fixup_3src_null_dest()
1998 unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE); in lower_simd_width() local
1999 dst = retype(dst_reg(VGRF, alloc.allocate(num_regs)), in lower_simd_width()
2645 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; in brw_compile_vs()
H A Dbrw_eu.h1667 int num_regs,
1672 int num_regs,
1677 int num_regs,
H A Dbrw_vec4_tcs.cpp464 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; in brw_compile_tcs()
H A Dbrw_fs.h407 uint8_t num_regs; member
H A Dbrw_vec4_gs_visitor.cpp826 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; in brw_compile_gs()
H A Dbrw_shader.cpp1425 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; in brw_compile_tes()
/third_party/node/deps/v8/src/compiler/backend/
H A Dregister-allocator.cc1981 int num_regs = config()->num_double_registers(); in FixedFPLiveRangeFor() local
1987 num_regs = config()->num_float_registers(); in FixedFPLiveRangeFor()
1991 num_regs = config()->num_simd128_registers(); in FixedFPLiveRangeFor()
1999 int offset = spill_mode == SpillMode::kSpillAtDefinition ? 0 : num_regs; in FixedFPLiveRangeFor()
2001 DCHECK(index < num_regs); in FixedFPLiveRangeFor()
2002 USE(num_regs); in FixedFPLiveRangeFor()
2020 int num_regs = config()->num_simd128_registers(); in FixedSIMD128LiveRangeFor() local
2023 int offset = spill_mode == SpillMode::kSpillAtDefinition ? 0 : num_regs; in FixedSIMD128LiveRangeFor()
2025 DCHECK(index < num_regs); in FixedSIMD128LiveRangeFor()
2026 USE(num_regs); in FixedSIMD128LiveRangeFor()
3996 GetFPRegisterSet(MachineRepresentation rep, int* num_regs, int* num_codes, const int** codes) const GetFPRegisterSet() argument
4013 GetSIMD128RegisterSet(int* num_regs, int* num_codes, const int** codes) const GetSIMD128RegisterSet() argument
4024 int num_regs = num_registers(); FindFreeRegistersForRange() local
4145 int num_regs = 0; // used only for the call to GetFPRegisterSet. PickRegisterThatIsAvailableLongest() local
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H A Dregister-allocator.h1488 void GetFPRegisterSet(MachineRepresentation rep, int* num_regs,
1490 void GetSIMD128RegisterSet(int* num_regs, int* num_codes,
/third_party/alsa-lib/src/topology/
H A Dctl.c475 if (strcmp(id, "num_regs") == 0) { in tplg_parse_control_bytes()
479 be->num_regs = ival; in tplg_parse_control_bytes()
480 tplg_dbg("\t%s: %d", id, be->num_regs); in tplg_parse_control_bytes()
578 if (err >= 0 && be->num_regs > 0) in tplg_save_control_bytes()
579 err = tplg_save_printf(dst, pfx, "\tnum_regs %u\n", be->num_regs); in tplg_save_control_bytes()
1163 be->num_regs = bytes_ctl->num_regs; in tplg_add_bytes()
1470 bt->num_regs = bc->num_regs; in tplg_decode_control_bytes1()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_perfcounter.c370 radv_get_num_counter_passes(const struct radv_physical_device *pdevice, unsigned num_regs, in radv_get_num_counter_passes() argument
378 for (unsigned i = 0; i < num_regs; ++i) { in radv_get_num_counter_passes()
914 unsigned num_regs = 0; in radv_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR() local
918 pPerformanceQueryCreateInfo->pCounterIndices, &num_regs, &regs); in radv_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR()
924 *pNumPasses = radv_get_num_counter_passes(pdevice, num_regs, regs); in radv_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR()
/third_party/alsa-lib/include/
H A Dtopology.h396 * num_regs "16" # Number of registers
926 int num_regs; /*!< number of registers */ member
/third_party/mesa3d/src/gallium/drivers/nouveau/nv30/
H A Dnvfx_fragprog.c32 int num_regs; member
178 if (fpc->num_regs < (dst.index + 1)) in emit_dst()
179 fpc->num_regs = dst.index + 1; in emit_dst()
1081 fpc->num_regs = 2; in _nvfx_fragprog_translate()
1125 fp->fp_control |= (fpc->num_regs-1)/2; in _nvfx_fragprog_translate()
1127 fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT; in _nvfx_fragprog_translate()
/third_party/alsa-lib/include/sound/uapi/
H A Dasoc.h448 __le32 num_regs; member
/third_party/node/deps/v8/src/execution/arm/
H A Dsimulator-arm.h331 int32_t ProcessPU(Instruction* instr, int num_regs, int operand_size,
H A Dsimulator-arm.cc1474 int32_t Simulator::ProcessPU(Instruction* instr, int num_regs, int reg_size, in ProcessPU() argument
1484 *end_address = rn_val + (num_regs * reg_size) - reg_size; in ProcessPU()
1485 rn_val = rn_val + (num_regs * reg_size); in ProcessPU()
1489 *start_address = rn_val - (num_regs * reg_size); in ProcessPU()
1496 *end_address = rn_val + (num_regs * reg_size); in ProcessPU()
1510 int num_regs = count_bits(rlist); in HandleRList() local
1515 ProcessPU(instr, num_regs, kPointerSize, &start_address, &end_address); in HandleRList()
1548 int num_regs; in HandleVList() local
1551 num_regs = instr->Immed8Value(); in HandleVList()
1553 num_regs in HandleVList()
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/third_party/node/deps/v8/src/execution/ppc/
H A Dsimulator-ppc.h270 void ProcessPUW(Instruction* instr, int num_regs, int operand_size,
/third_party/vixl/src/aarch64/
H A Dassembler-sve-aarch64.cc3833 void Assembler::SVELdSt234Helper(int num_regs, in SVELdSt234Helper() argument
3838 VIXL_ASSERT((num_regs >= 2) && (num_regs <= 4)); in SVELdSt234Helper()
3841 Instr num = (num_regs - 1) << 21; in SVELdSt234Helper()
3843 Instr mem_op = SVEMemOperandHelper(msize_in_bytes_log2, num_regs, addr); in SVELdSt234Helper()
4041 void Assembler::SVELd234Helper(int num_regs, in SVELd234Helper() argument
4059 SVELdSt234Helper(num_regs, zt1, pg, addr, op); in SVELd234Helper()
5052 int num_regs, in SVEMemOperandHelper()
5055 VIXL_ASSERT((num_regs >= 1) && (num_regs < in SVEMemOperandHelper()
5051 SVEMemOperandHelper(unsigned msize_in_bytes_log2, int num_regs, const SVEMemOperand& addr, bool is_load) SVEMemOperandHelper() argument
5158 SVESt234Helper(int num_regs, const ZRegister& zt1, const PRegister& pg, const SVEMemOperand& addr) SVESt234Helper() argument
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