/third_party/mesa3d/src/compiler/nir/ |
H A D | nir_opt_dead_write_vars.c | 51 nir_component_mask_t mask; 76 nir_deref_instr *dst, nir_component_mask_t mask) in update_unused_writes() 211 nir_component_mask_t mask = nir_intrinsic_write_mask(intrin); in remove_dead_write_vars_local() 234 nir_component_mask_t mask = (1 << glsl_get_vector_elements(dst->type)) - 1; in remove_dead_write_vars_local()
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H A D | nir_lower_ubo_vec4.c | 141 nir_component_mask_t low_channels = in nir_lower_ubo_vec4_lower() 143 nir_component_mask_t high_channels = in nir_lower_ubo_vec4_lower()
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H A D | nir_split_vars.c | 959 nir_component_mask_t all_comps; 961 nir_component_mask_t comps_read; 962 nir_component_mask_t comps_written; 964 nir_component_mask_t comps_kept; 1060 nir_component_mask_t comps_read, in mark_deref_used() 1061 nir_component_mask_t comps_written, in mark_deref_used() 1171 static nir_component_mask_t 1174 nir_component_mask_t comps = nir_intrinsic_write_mask(store); in get_non_self_referential_store_comps() 1322 nir_component_mask_t comps_kept = in shrink_vec_var_list() 1580 nir_component_mask_t write_mas in shrink_vec_var_access_impl() [all...] |
H A D | nir_lower_fragcolor.c | 81 nir_component_mask_t writemask = nir_intrinsic_write_mask(instr); in lower_fragcolor_instr()
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H A D | nir_opt_combine_stores.c | 55 nir_component_mask_t write_mask; 273 nir_component_mask_t prev_mask = nir_intrinsic_write_mask(prev_store); in update_combined_store()
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H A D | nir_opt_copy_prop_vars.c | 111 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); in value_equals_store_src() 194 nir_component_mask_t mask = (1 << glsl_get_vector_elements(payload->type)) - 1; in gather_vars_written() 299 nir_component_mask_t merged = (uintptr_t) new_entry->data | in gather_vars_written() 558 nir_component_mask_t available = 0; in load_from_ssa_entry_value() 1152 nir_component_mask_t full_mask = (1 << glsl_get_vector_elements(payload.instr->type)) - 1; in copy_prop_vars_block()
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H A D | nir.c | 130 nir_component_mask_can_reinterpret(nir_component_mask_t mask, in nir_component_mask_can_reinterpret() 165 nir_component_mask_t 166 nir_component_mask_reinterpret(nir_component_mask_t mask, in nir_component_mask_reinterpret() 175 nir_component_mask_t new_mask = 0; in nir_component_mask_reinterpret() 1862 nir_component_mask_t 1884 nir_component_mask_t 1887 nir_component_mask_t read_mask = 0; in nir_ssa_def_components_read() 3096 nir_component_mask_t 3099 nir_component_mask_t read_mask = 0; in nir_alu_instr_src_read_mask()
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H A D | nir_lower_input_attachments.c | 141 nir_component_mask_t load_result_mask = nir_component_mask(load_result_size); in try_lower_input_load()
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H A D | nir_lower_io_to_vector.c | 486 nir_component_mask_t vec4_comp_mask = in nir_lower_io_to_vector_impl() 556 nir_component_mask_t old_wrmask = nir_intrinsic_write_mask(intrin); in nir_lower_io_to_vector_impl()
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H A D | nir.h | 117 typedef uint16_t nir_component_mask_t; typedef 128 static inline nir_component_mask_t 138 bool nir_component_mask_can_reinterpret(nir_component_mask_t mask, 141 nir_component_mask_t 142 nir_component_mask_reinterpret(nir_component_mask_t mask, 1483 nir_component_mask_t 4211 nir_component_mask_t nir_src_components_read(const nir_src *src); 4212 nir_component_mask_t nir_ssa_def_components_read(const nir_ssa_def *def); 5192 typedef nir_component_mask_t (*nir_lower_non_uniform_access_callback)(const nir_src *, void *);
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H A D | nir_lower_non_uniform_access.c | 72 nir_component_mask_t channel_mask = ~0; in nu_handle_compare()
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H A D | nir_deref.c | 1246 nir_component_mask_t mask, in is_vector_bitcast_deref() 1308 nir_component_mask_t read_mask = in opt_load_vec_deref() 1349 nir_component_mask_t write_mask = nir_intrinsic_write_mask(store); in opt_store_vec_deref()
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H A D | nir_lower_io.c | 445 nir_component_mask_t write_mask, nir_alu_type src_type) in emit_store() 517 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); in lower_store() 529 nir_component_mask_t write_mask32 = 0; in lower_store() 1579 nir_ssa_def *value, nir_component_mask_t write_mask) in build_explicit_io_store() 1962 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); in nir_lower_explicit_io_instr() 1997 const nir_component_mask_t write_mask = 0; in nir_lower_explicit_io_instr()
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H A D | nir_builder.h | 497 nir_channels(nir_builder *b, nir_ssa_def *def, nir_component_mask_t mask) in nir_channels() 1358 nir_ssa_def *def, nir_component_mask_t write_mask) 1515 nir_ssa_def *value, nir_component_mask_t write_mask)
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H A D | nir_lower_system_values.c | 437 nir_component_mask_t is_zero = 0; in lower_compute_system_value_instr()
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H A D | nir_print.c | 277 nir_component_mask_t used_channels = 0; in print_alu_src()
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
H A D | sfn_nir_lower_tex.cpp | 176 (nir_component_mask_t)cmp_mask)); in lower_txl_txf_array_or_cube()
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/third_party/mesa3d/src/intel/compiler/ |
H A D | brw_nir_lower_mem_access_bit_sizes.c | 173 nir_component_mask_t writemask = nir_intrinsic_write_mask(intrin); in lower_mem_store_bit_size()
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H A D | brw_nir_rt_builder.h | 120 nir_ssa_def *value, nir_component_mask_t write_mask) in brw_nir_rt_store_scratch()
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/third_party/mesa3d/src/compiler/nir/tests/ |
H A D | vars_tests.cpp | 212 nir_ssa_def *value, nir_component_mask_t writemask) in nir_store_var_volatile() 1875 nir_component_mask_t mask = (1 << i) | (1 << (i + 1)); in TEST_F()
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/third_party/mesa3d/src/microsoft/compiler/ |
H A D | nir_to_dxil.c | 2623 nir_component_mask_t comps = nir_ssa_def_components_read(&intr->dest.ssa); in emit_load_global_invocation_id() 2646 nir_component_mask_t comps = nir_ssa_def_components_read(&intr->dest.ssa); in emit_load_local_invocation_id() 2684 nir_component_mask_t comps = nir_ssa_def_components_read(&intr->dest.ssa); in emit_load_local_workgroup_id()
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/third_party/mesa3d/src/amd/vulkan/ |
H A D | radv_pipeline.c | 4057 static nir_component_mask_t
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