| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 73 level_drm->nblk_y = level_ws->nblk_y; in surf_level_winsys_to_drm()
85 level_ws->nblk_y = level_drm->nblk_y; in surf_level_drm_to_winsys()
261 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8); in si_compute_cmask()
333 height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8); in si_compute_htile()
407 (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in radeon_winsys_surface_init()
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| /third_party/libdrm/radeon/ |
| H A D | radeon_surface.c | 177 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in surf_minify()
181 if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { in surf_minify()
187 surflevel->nblk_y = ALIGN(surflevel->nblk_y, yalign); in surf_minify()
192 surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y; in surf_minify()
586 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in eg_surf_minify()
590 if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { in eg_surf_minify()
596 surflevel->nblk_y = ALIGN(surflevel->nblk_y, mtileh); in eg_surf_minify()
602 mtile_ps = (mtile_pr * surflevel->nblk_y) / mtile in eg_surf_minify()
[all...] |
| H A D | radeon_surface.h | 76 uint32_t nblk_y; member
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | radeon_vce.c | 224 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); in si_vce_frame_offset()
455 align(tmp_surf->u.legacy.level[0].nblk_y, 32) in si_vce_create_encoder()
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| H A D | radeon_vce_40_2_2.c | 87 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw in create()
314 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
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| H A D | radeon_vce_50.c | 124 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
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| H A D | radeon_uvd_enc.c | 326 align(tmp_surf->u.legacy.level[0].nblk_y, 32) in radeon_uvd_create_encoder()
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| H A D | radeon_vce_52.c | 196 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw in create()
269 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
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| H A D | radeon_vcn_enc.c | 505 align(tmp_surf->u.legacy.level[0].nblk_y, 32) in radeon_create_encoder()
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| H A D | si_texture.c | 873 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " in si_print_texture_info()
879 tex->surface.u.legacy.level[i].nblk_y, tex->surface.u.legacy.level[i].mode, in si_print_texture_info()
887 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " in si_print_texture_info()
894 tex->surface.u.legacy.zs.stencil_level[i].nblk_y, in si_print_texture_info()
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| H A D | si_state.c | 2761 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in si_init_depth_surface()
2798 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1); in si_init_depth_surface()
2800 S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * levelinfo->nblk_y) / 64 - 1); in si_init_depth_surface()
3415 slice_tile_max = level_info->nblk_x * level_info->nblk_y / 64 - 1; in si_emit_framebuffer_state()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | radeon_vce.c | 235 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); in rvce_frame_offset()
456 align(tmp_surf->u.legacy.level[0].nblk_y, 32); in rvce_create_encoder()
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| H A D | r600_texture.c | 260 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4; in r600_init_surface()
645 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in r600_texture_get_fmask_info()
792 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8); in r600_texture_get_htile_size()
862 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " in r600_print_texture_info()
870 rtex->surface.u.legacy.level[i].nblk_y, in r600_print_texture_info()
880 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " in r600_print_texture_info()
888 rtex->surface.u.legacy.zs.stencil_level[i].nblk_y, in r600_print_texture_info()
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| H A D | r600_state.c | 837 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; in r600_init_color_surface()
1051 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; in r600_init_depth_surface()
1074 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; in r600_init_depth_surface()
2883 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); in r600_dma_copy_tile()
2902 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8); in r600_dma_copy_tile()
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| H A D | evergreen_state.c | 1141 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; in evergreen_set_color_surface_common()
1403 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in evergreen_init_depth_surface()
1409 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1); in evergreen_init_depth_surface()
1411 levelinfo->nblk_y / 64 - 1); in evergreen_init_depth_surface()
3804 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); in evergreen_dma_copy_tile()
3829 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8); in evergreen_dma_copy_tile()
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| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_surface.h | 96 unsigned nblk_y : 15; member
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| H A D | ac_surface.c | 698 surf_level->nblk_y = AddrSurfInfoOut->height; in gfx6_compute_level()
728 surf_level->nblk_y >= surf->prt_tile_height) { in gfx6_compute_level()
991 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8); in ac_compute_cmask()
2929 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4; in ac_surface_override_offset_stride()
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_device.c | 6301 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1; in radv_initialise_color_surface()
6702 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1); in radv_initialise_ds_surface()
6704 S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1); in radv_initialise_ds_surface()
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