Searched refs:msz (Results 1 - 3 of 3) sorted by relevance
/third_party/vixl/src/aarch64/ |
H A D | simulator-aarch64.cc | 12483 int msz = instr->ExtractBits(24, 23); in Simulator() local 12484 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz); in Simulator() 12510 int msz = instr->ExtractBits(24, 23); in Simulator() local 12511 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz); in Simulator() 12512 offset <<= msz; in Simulator() local 12536 int msz = instr->ExtractBits(24, 23); in Simulator() local 12541 addr.SetMsizeInBytesLog2(msz); in Simulator() 12543 SVEStructuredLoadHelper(SVEFormatFromLaneSizeInBytesLog2(msz), in Simulator() 12570 int msz = instr->ExtractBits(24, 23); in Simulator() local 12571 uint64_t offset = ReadXRegister(instr->GetRm()) * (1 << msz); in Simulator() 12650 int msz = 0; Simulator() local 12794 int msz = 0; Simulator() local 12972 int msz = instr->ExtractBits(24, 23); Simulator() local 13006 int msz = instr->ExtractBits(24, 23); Simulator() local [all...] |
H A D | disasm-aarch64.cc | 3723 unsigned msz = instr->ExtractBits(24, 23); in Disassembler() local 3725 if ((msz == kDRegSizeInBytesLog2) && sign_extend) { in Disassembler() 3728 VIXL_ASSERT(msz < ArrayLength(form_imm)); in Disassembler() 3729 form = form_imm[msz]; in Disassembler() 7078 int msz = instr->ExtractBits(24, 23); in Disassembler() local 7079 if (msz > 0) { in Disassembler() 7080 AppendToOutput(", lsl #%d", msz); in Disassembler()
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H A D | assembler-sve-aarch64.cc | 63 Instr msz = shift_amount << 10; in adr() local 82 Emit(op | msz | Rd(zd) | Rn(addr.GetVectorBase()) | in adr() 3842 Instr msz = msize_in_bytes_log2 << 23; in SVELdSt234Helper() local 3844 Emit(op | mem_op | msz | num | Rt(zt1) | PgLow8(pg)); in SVELdSt234Helper() 4035 Instr msz = ImmUnsignedField<24, 23>(msize_in_bytes_log2); in SVEScatterGatherHelper() local 4038 Emit(op | mem_op | msz | u | ff | Rt(zt) | PgLow8(pg)); in SVEScatterGatherHelper() 4257 // msz<24:23> = 00 | Zm<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> | Rn<9:5> in ldff1b() 4274 // msz<24:23> = 00 | imm5<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> | in ldff1b() 4293 // msz<24:23> = 11 | Zm<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> | Rn<9:5> in ldff1d() 4307 // msz<2 in ldff1d() [all...] |
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