Home
last modified time | relevance | path

Searched refs:mla (Results 1 - 25 of 44) sorted by relevance

12

/third_party/ffmpeg/libavcodec/arm/
H A Dflacdsp_arm.S65 mla r4, r7, r9, r4
68 mla r5, r6, r9, r5
77 mla r4, r7, r9, r4
106 mla r4, r7, r9, r4
108 mla r5, r6, r9, r5
110 mla r4, r6, r8, r4
112 mla r5, r7, r8, r5
116 mla r4, r7, r9, r4
118 mla r5, r7, r9, r5
121 mla r
[all...]
H A Djrevdct_arm.S90 mla r6, r5, r6, r7 @ r6 = tmp2
92 mla r2, r3, r2, r7 @ r2 = tmp3
119 mla r4, r10, r4, r8 @ r4 = 'z3'
121 mla r6, r9, r6, r8 @ r6 = 'z4'
123 mla r7, r10, r7, r2 @ r7 = tmp0 + z1
125 mla r5, r9, r5, r0 @ r5 = tmp1 + z2
127 mla r3, r10, r3, r0 @ r3 = tmp2 + z2
129 mla r1, r9, r1, r2 @ r1 = tmp3 + z1
222 mla r6, r5, r6, r1 @ r6 = tmp2
224 mla r
[all...]
H A Dmlpdsp_armv5te.S97 mla AC0, CO\index, ST\index, AC0
/third_party/ffmpeg/libavcodec/aarch64/
H A Dvp9mc_neon.S169 mla \dst1\().8h, v20.8h, v0.h[\offset]
171 mla \dst3\().8h, v22.8h, v0.h[\offset]
173 mla \dst2\().8h, v21.8h, v0.h[\offset]
174 mla \dst4\().8h, v23.8h, v0.h[\offset]
176 mla \dst1\().8h, v20.8h, v0.h[\offset]
177 mla \dst3\().8h, v22.8h, v0.h[\offset]
179 mla \dst1\().4h, v20.4h, v0.h[\offset]
180 mla \dst3\().4h, v22.4h, v0.h[\offset]
438 mla \dst1\().8h, \src3\().8h, v0.h[2]
439 mla \dst
[all...]
H A Dvc1dsp_neon.S54 mla v7.8h, v4.8h, v0.h[2] // 16 * src[8] + 15 * src[24] + 4 * src[56]
58 mla v18.8h, v4.8h, v0.h[1] // - 4 * src[8] + 9 * src[24] + 16 * src[56]
61 mla v3.8h, v16.8h, v0.h[0] // t3/2 = 16/2 * src[16] + 6/2 * src[48]
62 mla v7.8h, v6.8h, v0.h[1] // t1 = 16 * src[8] + 15 * src[24] + 9 * src[40] + 4 * src[56]
65 mla v20.8h, v17.8h, v0.h[1] // -t2 = - 15 * src[8] + 4 * src[24] + 16 * src[40] + 9 * src[56]
133 mla v16.8h, v20.8h, v0.h[1] // - 4 * src[8] + 9 * src[24] + 16 * src[56]
138 mla v2.8h, v20.8h, v0.h[2] // 16 * src[8] + 15 * src[24] + 4 * src[56]
140 mla v6.8h, v1.8h, v0.h[0] // t3/2 = 16/2 * src[16] + 6/2 * src[48]
143 mla v17.8h, v7.8h, v0.h[1] // -t2 = - 15 * src[8] + 4 * src[24] + 16 * src[40] + 9 * src[56]
150 mla v
[all...]
H A Dh264qpel_neon.S44 mla \d0\().8H, v2.8H, v6.H[1]
53 mla \d1\().8H, v0.8H, v6.H[1]
69 mla \d0\().8H, v2.8H, v6.H[1]
71 mla \d1\().8H, v0.8H, v6.H[1]
90 mla \r0\().8H, v0.8H, v6.H[1]
99 mla \r1\().8H, v4.8H, v6.H[1]
113 mla \d0\().8H, v2.8H, v6.H[1]
H A Dvp8dsp_neon.S731 mla v21.8h, v18.8h, v0.h[0]
732 mla v22.8h, v26.8h, v0.h[5]
763 mla v18.8h, v20.8h, v0.h[0]
764 mla v19.8h, v21.8h, v0.h[5]
765 mla v3.8h, v1.8h, v0.h[0]
766 mla v22.8h, v2.8h, v0.h[5]
791 mla \s0\().8h, \s2\().8h, v0.h[2]
792 mla v31.8h , \s5\().8h, v0.h[5]
793 mla \s3\().8h, \s1\().8h, v0.h[0]
794 mla \s
[all...]
H A Dvp9itxfm_16bpp_neon.S252 mla v22.4s, \c3\().4s, v0.s[2]
297 mla v16.4s, \c2\().4s, v1.s[1]
298 mla v16.4s, \c3\().4s, v1.s[2]
/third_party/libwebsockets/lib/core-net/client/
H A Dsort-dns.c236 int scopea, scopeb, scoped, mla, mlb; in lws_sort_dns_scomp() local
370 mla = lws_ipv6_prefix_match_len(sa6, dst); in lws_sort_dns_scomp()
373 if (mla > mlb) in lws_sort_dns_scomp()
/third_party/vixl/test/aarch64/
H A Dtest-api-movprfx-aarch64.cc187 __ mla(z11.VnS(), p1.Merging(), z11.VnS(), z27.VnS()); in TEST()
190 __ mla(z7.VnH(), p0.Merging(), z5.VnH(), z7.VnH()); in TEST()
767 __ mla(z14.VnD(), p6.Merging(), z28.VnD(), z11.VnD()); in TEST()
1482 __ mla(z8.VnS(), p6.Merging(), z4.VnS(), z26.VnS()); in TEST()
2064 __ mla(z2.VnH(), z0.VnH(), z1.VnH(), 0); in TEST()
2067 __ mla(z2.VnS(), z0.VnS(), z1.VnS(), 0); in TEST()
2070 __ mla(z2.VnD(), z0.VnD(), z1.VnD(), 0); in TEST()
2922 __ mla(z2.VnH(), z0.VnH(), z1.VnH(), 0); in TEST()
2925 __ mla(z2.VnS(), z0.VnS(), z1.VnS(), 0); in TEST()
2928 __ mla(z in TEST()
[all...]
H A Dtest-trace-aarch64.cc1245 __ mla(v29.V16B(), v7.V16B(), v26.V16B()); in GenerateTestSequenceNEON()
1246 __ mla(v6.V2S(), v4.V2S(), v14.V2S()); in GenerateTestSequenceNEON()
1247 __ mla(v9.V2S(), v11.V2S(), v0.S(), 2); in GenerateTestSequenceNEON()
1248 __ mla(v5.V4H(), v17.V4H(), v25.V4H()); in GenerateTestSequenceNEON()
1249 __ mla(v24.V4H(), v7.V4H(), v11.H(), 3); in GenerateTestSequenceNEON()
1250 __ mla(v12.V4S(), v3.V4S(), v4.V4S()); in GenerateTestSequenceNEON()
1251 __ mla(v10.V4S(), v7.V4S(), v7.S(), 3); in GenerateTestSequenceNEON()
1252 __ mla(v3.V8B(), v16.V8B(), v9.V8B()); in GenerateTestSequenceNEON()
1253 __ mla(v19.V8H(), v22.V8H(), v18.V8H()); in GenerateTestSequenceNEON()
1254 __ mla(v in GenerateTestSequenceNEON()
[all...]
H A Dtest-cpu-features-aarch64.cc1453 TEST_NEON(mla_0, mla(v0.V4H(), v1.V4H(), v2.H(), 1))
1454 TEST_NEON(mla_1, mla(v0.V8H(), v1.V8H(), v2.H(), 7))
1455 TEST_NEON(mla_2, mla(v0.V2S(), v1.V2S(), v2.S(), 0))
1456 TEST_NEON(mla_3, mla(v0.V4S(), v1.V4S(), v2.S(), 3))
1457 TEST_NEON(mla_4, mla(v0.V8B(), v1.V8B(), v2.V8B()))
1458 TEST_NEON(mla_5, mla(v0.V16B(), v1.V16B(), v2.V16B()))
1459 TEST_NEON(mla_6, mla(v0.V4H(), v1.V4H(), v2.V4H()))
1460 TEST_NEON(mla_7, mla(v0.V8H(), v1.V8H(), v2.V8H()))
1461 TEST_NEON(mla_8, mla(v0.V2S(), v1.V2S(), v2.V2S()))
1462 TEST_NEON(mla_9, mla(v
[all...]
H A Dtest-assembler-sve-aarch64.cc400 // The Mla macro automatically selects between mla, mad and movprfx + mla
447 int mla[] = {-84, 101, 33, 42};
450 int mla_da_expected[] = {mla[0], mla[1], za_inputs[2], mla[3]};
453 int mla_dn_expected[] = {mla[0], zn_inputs[1], mla[2], mla[3]};
456 int mla_dm_expected[] = {zm_inputs[0], mla[
[all...]
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-sve-aarch64.cc975 mla(zd, pg, zn, zm); in Mla()
989 mla(zd, pg, zn, zm); in Mla()
1862 V(Mla, mla, FourRegOneImmDestructiveHelper) \
H A Dassembler-aarch64.h2542 void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm);
2557 void mla(const VRegister& vd,
5025 void mla(const ZRegister& zda,
6121 void mla(const ZRegister& zda,
H A Dlogic-aarch64.cc691 LogicVRegister Simulator::mla(VectorFormat vform, in mla() function in vixl::aarch64::Simulator
801 LogicVRegister Simulator::mla(VectorFormat vform, in mla() function in vixl::aarch64::Simulator
808 return mla(vform, dst, dst, src1, dup_element(indexform, temp, src2, index)); in mla()
3852 mla(vform, dst, dst, temp1, temp2);
3873 mla(vform, dst, dst, temp1, temp2);
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc683 LogicVRegister Simulator::mla(VectorFormat vform, LogicVRegister dst, in mla() function in v8::internal::Simulator
719 LogicVRegister Simulator::mla(VectorFormat vform, LogicVRegister dst, in mla() function in v8::internal::Simulator
724 return mla(vform, dst, src1, dup_element(indexform, temp, src2, index)); in mla()
2639 mla(vform, dst, temp1, temp2); in umlal()
2649 mla(vform, dst, temp1, temp2); in umlal2()
2659 mla(vform, dst, temp1, temp2); in smlal()
2669 mla(vform, dst, temp1, temp2); in smlal2()
H A Dsimulator-arm64.h1595 LogicVRegister mla(VectorFormat vform, LogicVRegister dst,
1604 LogicVRegister mla(VectorFormat vform, LogicVRegister dst,
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h977 void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm,
2000 void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-arm64.h220 V(mla, Mla) \
388 V(mla, Mla) \
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc752 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); in DecodeType01()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.h242 void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm,
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc1074 __ mla(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1), in AssembleArchInstruction()
1250 __ mla(i.OutputRegister(1), i.InputRegister(0), i.InputRegister(3), in AssembleArchInstruction()
1252 __ mla(i.OutputRegister(1), i.InputRegister(2), i.InputRegister(1), in AssembleArchInstruction()
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h504 void mla(Register dst, Register src1, Register src2, Register srcA,
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/
H A Dassembler_arm.h508 // Moved to ARM32::AssemblerARM32::mla()
509 void mla(Register rd, Register rn, Register rm, Register ra,

Completed in 95 milliseconds

12