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Searched refs:ld2 (Results 1 - 24 of 24) sorted by relevance

/third_party/ffmpeg/libavcodec/aarch64/
H A Dmdct_neon.S40 ld2 {v16.2s,v17.2s}, [x7], x12 // d16=x,n1 d17=x,n0
41 ld2 {v0.2s,v1.2s}, [x2], #16 // d0 =m0,x d1 =m1,x
43 ld2 {v2.2s,v3.2s}, [x4], #16 // d2=c0,c1 d3=s0,s2
58 ld2 {v16.2s,v17.2s}, [x7], x12
59 ld2 {v0.2s,v1.2s}, [x2], #16
61 ld2 {v2.2s,v3.2s}, [x4], #16 // d2=c0,c1 d3=s0,s2
90 ld2 {v0.2s,v1.2s}, [x3], x7 // d0 =i1,r1 d1 =i0,r0
91 ld2 {v20.2s,v21.2s},[x6], #16 // d20=i2,r2 d21=i3,r3
92 ld2 {v16.2s,v17.2s},[x1], x7 // d16=c1,c0 d18=s1,s0
96 ld2 {v1
[all...]
H A Daacpsdsp_neon.S105 ld2 {v0.4S,v1.4S}, [x1], #32
106 ld2 {v2.2S,v3.2S}, [x1], #16
108 ld2 {v4.2S,v5.2S}, [x1], #16
109 ld2 {v6.4S,v7.4S}, [x1]
128 1: ld2 {v2.4S,v3.4S}, [x2], #32
129 ld2 {v4.2S,v5.2S}, [x2], #16
H A Dsbrdsp_neon.S78 ld2 {v0.4S, v1.4S}, [x0], #32
80 ld2 {v2.4S, v3.4S}, [x0], #32
84 ld2 {v0.4S, v1.4S}, [x0], #32
87 ld2 {v2.4S, v3.4S}, [x0], #32
145 1: ld2 {v0.4S, v1.4S}, [x1], x3
/third_party/alsa-lib/src/pcm/
H A Dmask_inline.h33 MASK_INLINE unsigned int ld2(uint32_t v) in ld2() function
125 return ld2(mask->bits[i]) + (i << 5); in snd_mask_max()
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_linear_sampler.c533 __m128i ld1, ld2, ld3; in fetch_bgra_clamp_linear() local
537 ld2 = _mm_cvtsi32_si128(data[addr[j].ui[2]]); in fetch_bgra_clamp_linear()
539 ld2 = _mm_unpacklo_epi32(ld2, ld3); in fetch_bgra_clamp_linear()
540 si[j] = _mm_unpacklo_epi64(si[j], ld2); in fetch_bgra_clamp_linear()
/third_party/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc974 __ ld2(v21.V16B(), v22.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON()
975 __ ld2(v21.V16B(), v22.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON()
976 __ ld2(v12.V16B(), v13.V16B(), MemOperand(x1, 32, PostIndex)); in GenerateTestSequenceNEON()
977 __ ld2(v14.V2D(), v15.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON()
978 __ ld2(v0.V2D(), v1.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON()
979 __ ld2(v12.V2D(), v13.V2D(), MemOperand(x1, 32, PostIndex)); in GenerateTestSequenceNEON()
980 __ ld2(v27.V2S(), v28.V2S(), MemOperand(x0)); in GenerateTestSequenceNEON()
981 __ ld2(v2.V2S(), v3.V2S(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON()
982 __ ld2(v12.V2S(), v13.V2S(), MemOperand(x1, 16, PostIndex)); in GenerateTestSequenceNEON()
983 __ ld2(v in GenerateTestSequenceNEON()
[all...]
H A Dtest-cpu-features-aarch64.cc1148 TEST_NEON(ld2_0, ld2(v0.V8B(), v1.V8B(), MemOperand(x2)))
1149 TEST_NEON(ld2_1, ld2(v0.V16B(), v1.V16B(), MemOperand(x2)))
1150 TEST_NEON(ld2_2, ld2(v0.V4H(), v1.V4H(), MemOperand(x2)))
1151 TEST_NEON(ld2_3, ld2(v0.V8H(), v1.V8H(), MemOperand(x2)))
1152 TEST_NEON(ld2_4, ld2(v0.V2S(), v1.V2S(), MemOperand(x2)))
1153 TEST_NEON(ld2_5, ld2(v0.V4S(), v1.V4S(), MemOperand(x2)))
1154 TEST_NEON(ld2_6, ld2(v0.V2D(), v1.V2D(), MemOperand(x2)))
1155 TEST_NEON(ld2_7, ld2(v0.V8B(), v1.V8B(), MemOperand(x2, 16, PostIndex)))
1156 TEST_NEON(ld2_8, ld2(v0.V16B(), v1.V16B(), MemOperand(x2, 32, PostIndex)))
1157 TEST_NEON(ld2_9, ld2(v
[all...]
/third_party/ffmpeg/libswscale/aarch64/
H A Dyuv2rgb_neon.S80 ld2 {v16.8B, v17.8B}, [x6], #16
86 ld2 {v16.8B, v17.8B}, [x6], #16
/third_party/node/deps/openssl/openssl/crypto/modes/asm/
H A Dghash-ia64.pl322 ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
351 ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
376 { .mfi; ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
396 { .mmi; ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
/third_party/openssl/crypto/modes/asm/
H A Dghash-ia64.pl322 ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
351 ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
376 { .mfi; ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
396 { .mmi; ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_peephole.cpp3985 Instruction *ld2 = NULL; // can get at most 2 loads in checkSplitLoad() local
4053 ld2 = cloneShallow(func, ld1); in checkSplitLoad()
4054 updateLdStOffset(ld2, addr2, func); in checkSplitLoad()
4055 ld2->setType(typeOfSize(size2)); in checkSplitLoad()
4057 ld2->setDef(d, (d < n2) ? def2[d] : NULL); in checkSplitLoad()
4059 ld1->bb->insertAfter(ld1, ld2); in checkSplitLoad()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h1858 void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
1861 void ld2(const VRegister& vt, const VRegister& vt2, int lane,
H A Dmacro-assembler-arm64.h1660 ld2(vt, vt2, src); in Ld2()
1665 ld2(vt, vt2, lane, src); in Ld2()
H A Dassembler-arm64.cc2374 void Assembler::ld2(const VRegister& vt, const VRegister& vt2, in ld2() function in v8::internal::Assembler
2382 void Assembler::ld2(const VRegister& vt, const VRegister& vt2, int lane, in ld2() function in v8::internal::Assembler
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.h1552 void ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2,
1554 void ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2,
H A Dsimulator-arm64.cc4911 ld2(vf, vreg(reg[0]), vreg(reg[1]), addr[0]);
5155 ld2(vf, vreg(rt), vreg(rt2), lane, addr);
H A Dsimulator-logic-arm64.cc366 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2() function in v8::internal::Simulator
380 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2() function in v8::internal::Simulator
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.h3329 void ld2(VectorFormat vform,
3333 void ld2(VectorFormat vform,
H A Dassembler-aarch64.h2897 void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
2900 void ld2(const VRegister& vt,
H A Dassembler-aarch64.cc2630 void Assembler::ld2(const VRegister& vt, in ld2() function in vixl::aarch64::Assembler
2641 void Assembler::ld2(const VRegister& vt, in ld2() function in vixl::aarch64::Assembler
H A Dlogic-aarch64.cc224 void Simulator::ld2(VectorFormat vform, in ld2() function in vixl::aarch64::Simulator
241 void Simulator::ld2(VectorFormat vform, in ld2() function in vixl::aarch64::Simulator
H A Dmacro-assembler-aarch64.h3387 ld2(vt, vt2, src); in Ld2()
3395 ld2(vt, vt2, lane, src); in Ld2()
H A Dsimulator-aarch64.cc8289 ld2(vf, ReadVRegister(reg[0]), ReadVRegister(reg[1]), addr[0]); in Simulator()
8528 ld2(vf, ReadVRegister(rt), ReadVRegister(rt2), lane, addr); in Simulator()
H A Dassembler-sve-aarch64.cc4072 void Assembler::ld2##MSZ(const ZRegister& zt1, \

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