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Searched refs:lane_size_in_bits (Results 1 - 10 of 10) sorted by relevance

/third_party/vixl/test/aarch64/
H A Dtest-assembler-sve-aarch64.cc370 static void MlaMlsHelper(Test* config, unsigned lane_size_in_bits) {
379 ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
380 ZRegister za = z1.WithLaneSize(lane_size_in_bits);
381 ZRegister zn = z2.WithLaneSize(lane_size_in_bits);
382 ZRegister zm = z3.WithLaneSize(lane_size_in_bits);
395 Initialise(&masm, p0.WithLaneSize(lane_size_in_bits), p0_inputs);
396 Initialise(&masm, p1.WithLaneSize(lane_size_in_bits), p1_inputs);
397 Initialise(&masm, p2.WithLaneSize(lane_size_in_bits), p2_inputs);
398 Initialise(&masm, p3.WithLaneSize(lane_size_in_bits), p3_inputs);
402 ZRegister mla_da_result = z10.WithLaneSize(lane_size_in_bits);
3753 CntHelper(Test* config, CntFn cnt, int multiplier, int lane_size_in_bits, int64_t acc_value = 0, bool is_increment = true) CntHelper() argument
3797 IncHelper(Test* config, CntFn cnt, int multiplier, int lane_size_in_bits, int64_t acc_value) IncHelper() argument
3805 DecHelper(Test* config, CntFn cnt, int multiplier, int lane_size_in_bits, int64_t acc_value) DecHelper() argument
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H A Dtest-utils-aarch64.h205 inline int GetSVELaneCount(int lane_size_in_bits) const {
206 VIXL_ASSERT(lane_size_in_bits > 0);
207 VIXL_ASSERT((dump_.vl_ % lane_size_in_bits) == 0);
208 uint64_t count = dump_.vl_ / lane_size_in_bits;
/third_party/vixl/src/aarch64/
H A Dinstructions-aarch64.cc630 int lane_size_in_bits = 1 << (lane_size_in_bytes_log2 + 3); in GetSVEImmLogical() local
631 return DecodeImmBitMask(n, imm_s, imm_r, lane_size_in_bits); in GetSVEImmLogical()
1142 VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits) { in ScalarFormatFromLaneSize() argument
1143 switch (lane_size_in_bits) { in ScalarFormatFromLaneSize()
1193 VectorFormat SVEFormatFromLaneSizeInBits(int lane_size_in_bits) { in SVEFormatFromLaneSizeInBits() argument
1194 switch (lane_size_in_bits) { in SVEFormatFromLaneSizeInBits()
1200 return SVEFormatFromLaneSizeInBytes(lane_size_in_bits / kBitsPerByte); in SVEFormatFromLaneSizeInBits()
H A Dregisters-aarch64.h633 explicit ZRegister(int code, int lane_size_in_bits = kUnknownSize)
637 EncodeSizeInBits(lane_size_in_bits)) {
721 PRegisterWithLaneSize(int code, int lane_size_in_bits)
722 : PRegister(code, EncodeSizeInBits(lane_size_in_bits)) {
H A Dinstructions-aarch64.h775 VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits);
779 VectorFormat SVEFormatFromLaneSizeInBits(int lane_size_in_bits);
H A Dlogic-aarch64.cc901 int lane_size_in_bits) const { in PolynomialMult()
902 VIXL_ASSERT(static_cast<unsigned>(lane_size_in_bits) <= kSRegSize); in PolynomialMult()
903 VIXL_ASSERT(IsUintN(lane_size_in_bits, op1)); in PolynomialMult()
904 VIXL_ASSERT(IsUintN(lane_size_in_bits, op2)); in PolynomialMult()
906 for (int i = 0; i < lane_size_in_bits; ++i) { in PolynomialMult()
1806 int lane_size_in_bits = LaneSizeInBitsFromFormat(vform);
1813 result[i] = CountLeadingSignBits(src.Int(vform, i), lane_size_in_bits);
1827 int lane_size_in_bits = LaneSizeInBitsFromFormat(vform);
1834 result[i] = CountLeadingZeros(src.Uint(vform, i), lane_size_in_bits);
1860 int lane_size_in_bits
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H A Dassembler-aarch64.cc5484 int lane_size_in_bits = vn.GetLaneSizeInBits();
5485 VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits));
5486 NEONShiftImmediate(vd, vn, op, (lane_size_in_bits + shift) << 16);
5494 int lane_size_in_bits = vn.GetLaneSizeInBits();
5495 VIXL_ASSERT((shift >= 1) && (shift <= lane_size_in_bits));
5496 NEONShiftImmediate(vd, vn, op, ((2 * lane_size_in_bits) - shift) << 16);
5504 int lane_size_in_bits = vn.GetLaneSizeInBits();
5505 VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits));
5506 int immh_immb = (lane_size_in_bits + shift) << 16;
5522 int lane_size_in_bits
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H A Dassembler-sve-aarch64.cc368 Instr Assembler::EncodeSVEShiftLeftImmediate(int shift, int lane_size_in_bits) { in EncodeSVEShiftLeftImmediate() argument
369 VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits)); in EncodeSVEShiftLeftImmediate()
370 return lane_size_in_bits + shift; in EncodeSVEShiftLeftImmediate()
374 int lane_size_in_bits) { in EncodeSVEShiftRightImmediate()
375 VIXL_ASSERT((shift > 0) && (shift <= lane_size_in_bits)); in EncodeSVEShiftRightImmediate()
376 return (2 * lane_size_in_bits) - shift; in EncodeSVEShiftRightImmediate()
373 EncodeSVEShiftRightImmediate(int shift, int lane_size_in_bits) EncodeSVEShiftRightImmediate() argument
H A Dassembler-aarch64.h8024 Instr EncodeSVEShiftLeftImmediate(int shift, int lane_size_in_bits);
8026 Instr EncodeSVEShiftRightImmediate(int shift, int lane_size_in_bits);
H A Dsimulator-aarch64.h3319 int lane_size_in_bits) const;

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