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Searched refs:indirect_offset (Results 1 - 25 of 41) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_tcs.cpp156 const src_reg &indirect_offset) in emit_input_urb_read()
165 indirect_offset); in emit_input_urb_read()
178 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in emit_input_urb_read()
191 const src_reg &indirect_offset) in emit_output_urb_read()
198 brw_imm_ud(dst.writemask << first_component), indirect_offset); in emit_output_urb_read()
218 const src_reg &indirect_offset) in emit_urb_write()
227 brw_imm_ud(writemask), indirect_offset); in emit_urb_write()
257 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
267 first_component, indirect_offset); in nir_emit_intrinsic()
275 src_reg indirect_offset in nir_emit_intrinsic() local
152 emit_input_urb_read(const dst_reg &dst, const src_reg &vertex_index, unsigned base_offset, unsigned first_component, const src_reg &indirect_offset) emit_input_urb_read() argument
188 emit_output_urb_read(const dst_reg &dst, unsigned base_offset, unsigned first_component, const src_reg &indirect_offset) emit_output_urb_read() argument
215 emit_urb_write(const src_reg &value, unsigned writemask, unsigned base_offset, const src_reg &indirect_offset) emit_urb_write() argument
292 src_reg indirect_offset = get_indirect_offset(instr); nir_emit_intrinsic() local
303 imm_offset, indirect_offset); nir_emit_intrinsic() local
[all...]
H A Dbrw_vec4_tcs.h61 const src_reg &indirect_offset);
65 const src_reg &indirect_offset);
68 unsigned base_offset, const src_reg &indirect_offset);
H A Dbrw_vec4_tes.cpp154 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
159 if (indirect_offset.file != BAD_FILE) { in nir_emit_intrinsic()
167 retype(indirect_offset, BRW_REGISTER_TYPE_UD), in nir_emit_intrinsic()
H A Dbrw_reg.h235 int indirect_offset:10; /* relative addressing offset */ member
434 reg.indirect_offset = 0; in brw_reg()
1144 reg.indirect_offset = offset;
1154 reg.indirect_offset = offset;
1165 reg.indirect_offset = offset;
H A Dbrw_ir.h77 using brw_reg::indirect_offset;
H A Dbrw_fs_nir.cpp2614 fs_reg indirect_offset = get_nir_src(offset_src);
2647 srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset;
2914 fs_reg indirect_offset = get_indirect_offset(instr);
2932 if (indirect_offset.file == BAD_FILE) {
2951 srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset;
2976 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
2988 fs_reg indirect_offset = get_indirect_offset(instr);
2995 if (indirect_offset.file == BAD_FILE) {
3029 srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset;
3057 fs_reg indirect_offset
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/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_const.h584 unsigned indirect_offset; variable
594 if (info->indirect_offset & 0xf) {
598 indirect_offset = 0;
601 info->indirect_offset, 3);
604 indirect_offset = info->indirect_offset;
607 emit_const_prsc(ring, v, offset * 4, indirect_offset, 16, indirect);
/third_party/mesa3d/src/mesa/state_tracker/
H A Dst_draw.h94 GLsizeiptr indirect_offset,
H A Dst_draw.c239 GLsizeiptr indirect_offset, in st_indirect_draw_vbo()
276 indirect.offset = indirect_offset; in st_indirect_draw_vbo()
236 st_indirect_draw_vbo(struct gl_context *ctx, GLuint mode, struct gl_buffer_object *indirect_data, GLsizeiptr indirect_offset, unsigned draw_count, unsigned stride, struct gl_buffer_object *indirect_draw_count, GLsizeiptr indirect_draw_count_offset, const struct _mesa_index_buffer *ib, bool primitive_restart, unsigned restart_index) st_indirect_draw_vbo() argument
/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard_compile.c1198 nir_src *indirect_offset, in emit_ubo_read()
1229 if (indirect_offset) { in emit_ubo_read()
1230 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_ubo_read()
1242 if (indirect_offset && indirect_offset->is_ssa && !indirect_shift) in emit_ubo_read()
1243 mir_set_ubo_offset(&ins, indirect_offset, offset); in emit_ubo_read()
1422 nir_src *indirect_offset, nir_alu_type type, bool flat) in emit_varying_read()
1447 if (indirect_offset) { in emit_varying_read()
1448 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_varying_read()
1837 nir_src *indirect_offset in emit_intrinsic() local
1193 emit_ubo_read( compiler_context *ctx, nir_instr *instr, unsigned dest, unsigned offset, nir_src *indirect_offset, unsigned indirect_shift, unsigned index, unsigned nr_comps) emit_ubo_read() argument
1418 emit_varying_read( compiler_context *ctx, unsigned dest, unsigned offset, unsigned nr_comp, unsigned component, nir_src *indirect_offset, nir_alu_type type, bool flat) emit_varying_read() argument
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/third_party/mesa3d/src/intel/tools/
H A Di965_gram.y1739 // brw_reg set indirect_offset to 0 so set it to valid value
1740 $$.indirect_offset = $3.indirect_offset;
1776 $$.indirect_offset = $2;
1808 $$.indirect_offset = $3.indirect_offset;
1827 $$.indirect_offset = $3.indirect_offset;
/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_pipe_cs.c213 info->indirect_offset)); in svga_launch_grid()
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_compute.c177 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
/third_party/mesa3d/src/gallium/drivers/etnaviv/tests/
H A Dlower_ubo_tests.cpp169 TEST_F(nir_lower_ubo_test, indirect_offset) in TEST_F()
/third_party/mesa3d/src/gallium/drivers/softpipe/
H A Dsp_compute.c151 info->indirect_offset, in fill_grid_size()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_compute.c184 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_compute.c192 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0);
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_compute.c472 uint32_t offset = res->offset + info->indirect_offset; in nvc0_launch_grid()
512 uint32_t offset = res->offset + info->indirect_offset; in nvc0_compute_update_indirect_invocations()
/third_party/mesa3d/src/gallium/include/pipe/
H A Dp_state.h992 unsigned indirect_offset; /**< must be 4 byte aligned */ member
/third_party/mesa3d/src/mesa/main/
H A Dcompute.c370 info.indirect_offset = indirect; in dispatch_compute_indirect()
/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_draw.cpp1314 unsigned indirect_offset = info->indirect_offset; in d3d12_launch_grid() local
1315 if (indirect && update_dispatch_indirect_with_sysvals(ctx, &indirect, &indirect_offset, &patched_indirect)) in d3d12_launch_grid()
1367 indirect_arg_offset = indirect_offset + buf_offset; in d3d12_launch_grid()
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_program.c95 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); in indirect_uniform_load() local
99 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0)); in indirect_uniform_load()
100 indirect_offset = qir_MIN_NOIMM(c, indirect_offset, in indirect_uniform_load()
104 indirect_offset, in indirect_uniform_load()
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_draw.c340 grid_ref->offset = grid->indirect_offset; in iris_update_grid_size_resource()
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_draw.c458 grid_ref->offset = grid->indirect_offset; in crocus_update_grid_size_resource()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_compute.c777 info->indirect_offset + 4 * i); in si_setup_nir_user_data()
870 radeon_emit(info->indirect_offset); in si_emit_dispatch_packets()

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