| /third_party/musl/tools/ |
| H A D | add-cfi.i386.awk | 39 function get_reg() { function
162 register = get_reg()
172 register = get_reg()
203 /(dec|inc|not|neg|pop) %e?([abcd][hlx]|si|di|bp)/ { trashed(get_reg()) }
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| H A D | add-cfi.x86_64.awk | 34 function get_reg() { function
148 register = get_reg()
158 register = get_reg()
190 /(dec|inc|not|neg|pop) %[er]?([abcd][xlh]|si|di|bp|8|9|10|11|12|13|14|15)/ { trashed(get_reg()) }
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| H A D | ir2_assemble.c | 65 struct ir2_reg_component *comp = get_reg(instr)->comp; in alu_swizzle()
105 struct ir2_reg_component *comp = get_reg(instr)->comp; in alu_write_mask()
131 struct ir2_reg_component *comp = get_reg(instr)->comp; in fetch_dst_swiz()
147 return get_reg(instr)->idx; in dst_to_reg()
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| H A D | ir2.c | 305 ra_reg(ctx, get_reg(instr), -1, false, 0); in sched_next()
379 ra_reg(ctx, get_reg(instr_v), -1, is_export(instr_v), in sched_next()
383 ra_reg(ctx, get_reg(instr_s), -1, is_export(instr_s), in sched_next()
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| H A D | ir2_private.h | 338 get_reg(struct ir2_instr *instr) in get_reg() function
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| /third_party/libunwind/libunwind/include/ |
| H A D | libunwind-common.h | 250 #define unw_get_reg UNW_OBJ(get_reg)
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | r3xx_vertprog.c | 593 static int get_reg(struct radeon_compiler *c, struct temporary_allocation *ta, bool *hwtemps, in get_reg() function
675 inst->U.I.SrcReg[i].Index = get_reg(c, ta, hwtemps, orig); in allocate_temporary_registers()
685 inst->U.I.DstReg.Index = get_reg(c, ta, hwtemps, orig); in allocate_temporary_registers()
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| /third_party/ltp/tools/sparse/sparse-src/ |
| H A D | compile-i386.c | 350 static struct storage *get_reg(struct regclass *class) in get_reg() function
377 reg = get_reg(class); in get_reg_value()
387 return get_reg(get_regclass_bits(bit_size)); in temp_from_bits()
1264 reg1 = get_reg(®class_32_8); in emit_compare()
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| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_register_allocation.cpp | 1605 get_reg(ra_ctx& ctx, RegisterFile& reg_file, Temp temp, in get_reg() function
1710 return get_reg(ctx, reg_file, temp, parallelcopies, instr, operand_index); in get_reg()
1814 /* too many moves: try the generic get_reg() function */ in get_reg_create_vector()
1816 return get_reg(ctx, reg_file, temp, parallelcopies, instr); in get_reg_create_vector()
1845 /* use the fallback algorithm in get_reg() */ in get_reg_create_vector()
1846 return get_reg(ctx, reg_file, temp, parallelcopies, instr); in get_reg_create_vector()
1981 dst = get_reg(ctx, register_file, operand.getTemp(), parallelcopy, instr, operand_index); in get_reg_for_operand()
1997 PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, phi); in get_reg_phi()
2909 PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, instr); in register_allocation()
2917 definition->setFixed(get_reg(ct in register_allocation()
[all...] |
| /third_party/mesa3d/src/freedreno/ir3/ |
| H A D | ir3_ra.c | 1371 get_reg(struct ra_ctx *ctx, struct ra_file *file, struct ir3_register *reg) in get_reg() function
1556 /* All the hard work is done by get_reg here. */ in allocate_dst()
1557 physreg_t physreg = get_reg(ctx, file, dst); in allocate_dst()
1853 * a duplication of much of the logic in get_reg(). This also opens another
1890 * some of the get_reg() machinery as-if the source is a destination. in handle_chmask()
1987 physreg = get_reg(ctx, file, def); in handle_phi()
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