/third_party/vixl/test/aarch32/ |
H A D | test-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc | 116 {{ge, r1, 250}, true, ge, "ge r1 250", "ge_r1_250"}, 125 {{ge, r6, 203}, true, ge, "ge r6 203", "ge_r6_203"}, 132 {{ge, r4, 133}, true, ge, "ge r4 133", "ge_r4_133"}, 151 {{ge, r [all...] |
H A D | test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc | 735 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"}, 736 {{ge, r0, r1}, true, ge, "ge r0 r1", "ge_r0_r1"}, 737 {{ge, r0, r2}, true, ge, "ge r0 r2", "ge_r0_r2"}, 738 {{ge, r [all...] |
H A D | test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc | 735 {{ge, r0, r0, 0}, true, ge, "ge r0 r0 0", "ge_r0_r0_0"}, 736 {{ge, r0, r1, 0}, true, ge, "ge r0 r1 0", "ge_r0_r1_0"}, 737 {{ge, r0, r2, 0}, true, ge, "ge r0 r2 0", "ge_r0_r2_0"}, 738 {{ge, r [all...] |
H A D | test-assembler-cond-rd-operand-rn-in-it-block-t32.cc | 2346 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"}, 2347 {{ge, r0, r1}, true, ge, "ge r0 r1", "ge_r0_r1"}, 2348 {{ge, r0, r2}, true, ge, "ge r0 r2", "ge_r0_r2"}, 2349 {{ge, r [all...] |
H A D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc | 112 {{ge, r7, r5, 7}, true, ge, "ge r7 r5 7", "ge_r7_r5_7"}, 118 {{ge, r7, r1, 0}, true, ge, "ge r7 r1 0", "ge_r7_r1_0"}, 119 {{ge, r2, r0, 0}, true, ge, "ge r2 r0 0", "ge_r2_r0_0"}, 120 {{ge, r [all...] |
H A D | test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc | 735 {{ge, r0, r0, r0}, true, ge, "ge r0 r0 r0", "ge_r0_r0_r0"}, 736 {{ge, r0, r1, r0}, true, ge, "ge r0 r1 r0", "ge_r0_r1_r0"}, 737 {{ge, r0, r2, r0}, true, ge, "ge r0 r2 r0", "ge_r0_r2_r0"}, 738 {{ge, r [all...] |
H A D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc | 100 {{ge, r6, r6, 181}, true, ge, "ge r6 r6 181", "ge_r6_r6_181"}, 103 {{ge, r4, r4, 195}, true, ge, "ge r4 r4 195", "ge_r4_r4_195"}, 124 {{ge, r6, r6, 88}, true, ge, "ge r6 r6 88", "ge_r6_r6_88"}, 126 {{ge, r [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc | 99 {{ge, r5, r0, LSL, 3}, true, ge, "ge r5 r0 LSL 3", "ge_r5_r0_LSL_3"}, 101 {{ge, r6, r6, LSL, 28}, true, ge, "ge r6 r6 LSL 28", "ge_r6_r6_LSL_28"}, 105 {{ge, r0, r1, LSL, 6}, true, ge, "ge r0 r1 LSL 6", "ge_r0_r1_LSL_6"}, 126 {{ge, r [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc | 245 {{ge, r13, r13, r0}, true, ge, "ge r13 r13 r0", "ge_r13_r13_r0"}, 246 {{ge, r13, r13, r1}, true, ge, "ge r13 r13 r1", "ge_r13_r13_r1"}, 247 {{ge, r13, r13, r2}, true, ge, "ge r13 r13 r2", "ge_r13_r13_r2"}, 248 {{ge, r1 [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc | 96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"}, 118 {{ge, r4, r4, ASR, r1}, true, ge, "ge r4 r4 ASR r1", "ge_r4_r4_ASR_r1"}, 122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"}, 127 {{ge, r [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc | 106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"}, 113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"}, 135 {{ge, r3, r3, r7}, true, ge, "ge r3 r3 r7", "ge_r3_r3_r7"}, 152 {{ge, r [all...] |
H A D | test-macro-assembler-cond-rd-rn-pc-a32.cc | 397 {{ge, r0, r15}, "ge, r0, r15", "ge_r0_r15"}, 398 {{ge, r1, r15}, "ge, r1, r15", "ge_r1_r15"}, 399 {{ge, r2, r15}, "ge, r2, r15", "ge_r2_r15"}, 400 {{ge, r3, r15}, "ge, r3, r15", "ge_r3_r15"}, 401 {{ge, r4, r15}, "ge, r [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 122 {{ge, r6, r0, ROR, 16}, false, al, "ge r6 r0 ROR 16", "ge_r6_r0_ROR_16"}, 124 {{ge, r10, r13, ROR, 31}, 127 "ge r10 r13 ROR 31", 164 {{ge, r9, r3, ROR, 4}, false, al, "ge r9 r3 ROR 4", "ge_r9_r3_ROR_4"}, 187 {{ge, r4, r8, ROR, 29}, false, al, "ge r4 r8 ROR 29", "ge_r4_r8_ROR_29"}, 211 {{ge, r2, r0, LSL, 18}, false, al, "ge r [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc | 124 {{ge, r1, r3, r4}, true, ge, "ge r1 r3 r4", "ge_r1_r3_r4"}, 127 {{ge, r6, r2, r3}, true, ge, "ge r6 r2 r3", "ge_r6_r2_r3"}, 129 {{ge, r7, r2, r4}, true, ge, "ge r7 r2 r4", "ge_r7_r2_r4"}, 132 {{ge, r [all...] |
H A D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc | 96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"}, 104 {{ge, r5, r0, ASR, 23}, true, ge, "ge r5 r0 ASR 23", "ge_r5_r0_ASR_23"}, 137 {{ge, r7, r3, ASR, 28}, true, ge, "ge r7 r3 ASR 28", "ge_r7_r3_ASR_28"}, 139 {{ge, r [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc | 107 {{ge, r7, r7, r12}, true, ge, "ge r7 r7 r12", "ge_r7_r7_r12"}, 116 {{ge, r12, r12, r2}, true, ge, "ge r12 r12 r2", "ge_r12_r12_r2"}, 120 {{ge, r14, r14, r4}, true, ge, "ge r14 r14 r4", "ge_r14_r14_r4"}, 125 {{ge, r [all...] |
H A D | test-macro-assembler-cond-rd-rn-a32.cc | 116 {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"}, 130 {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"}, 142 {{ge, r0, r14}, "ge, r0, r14", "ge_r0_r14"}, 194 {{ge, r1, r6}, "ge, r1, r6", "ge_r1_r6"}, 218 {{ge, r2, r8}, "ge, r [all...] |
H A D | test-macro-assembler-cond-rd-rn-t32.cc | 116 {{ge, r0, r10}, "ge, r0, r10", "ge_r0_r10"}, 130 {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"}, 142 {{ge, r0, r14}, "ge, r0, r14", "ge_r0_r14"}, 194 {{ge, r1, r6}, "ge, r1, r6", "ge_r1_r6"}, 218 {{ge, r2, r8}, "ge, r [all...] |
H A D | test-assembler-cond-rd-operand-rn-a32.cc | 116 {{ge, r12, r3}, false, al, "ge r12 r3", "ge_r12_r3"}, 118 {{ge, r7, r13}, false, al, "ge r7 r13", "ge_r7_r13"}, 120 {{ge, r9, r3}, false, al, "ge r9 r3", "ge_r9_r3"}, 135 {{ge, r13, r5}, false, al, "ge r13 r5", "ge_r13_r5"}, 137 {{ge, r7, r11}, false, al, "ge r [all...] |
H A D | test-assembler-cond-rd-operand-rn-identical-low-registers-in-it-block-t32.cc | 173 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"}, 174 {{ge, r1, r1}, true, ge, "ge r1 r1", "ge_r1_r1"}, 175 {{ge, r2, r2}, true, ge, "ge r2 r2", "ge_r2_r2"}, 176 {{ge, r [all...] |
H A D | test-assembler-cond-rd-rn-operand-rm-rn-is-sp-in-it-block-t32.cc | 175 {{ge, r0, r13, r0}, true, ge, "ge r0 r13 r0", "ge_r0_r13_r0"}, 176 {{ge, r1, r13, r1}, true, ge, "ge r1 r13 r1", "ge_r1_r13_r1"}, 177 {{ge, r2, r13, r2}, true, ge, "ge r2 r13 r2", "ge_r2_r13_r2"}, 178 {{ge, r [all...] |
H A D | test-assembler-cond-rd-operand-const-can-use-pc-a32.cc | 138 {{ge, r9, 0xac000002}, false, al, "ge r9 0xac000002", "ge_r9_0xac000002"}, 165 {{ge, r0, 0x0ff00000}, false, al, "ge r0 0x0ff00000", "ge_r0_0x0ff00000"}, 192 {{ge, r10, 0x00ff0000}, 195 "ge r10 0x00ff0000", 283 {{ge, r10, 0x002ac000}, 286 "ge r10 0x002ac000", 330 {{ge, r7, 0x000003fc}, false, al, "ge r [all...] |
/third_party/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_shader_llvm.c | 154 if (ctx->shader->key.ge.as_ls) in si_llvm_create_func() 156 else if (ctx->shader->key.ge.as_es || ctx->shader->key.ge.as_ngg) in si_llvm_create_func() 191 if (ctx->stage <= MESA_SHADER_GEOMETRY && ctx->shader->key.ge.as_ngg && in si_llvm_create_func() 228 (shader->key.ge.as_ls || ctx->stage == MESA_SHADER_TESS_CTRL)) { in si_llvm_create_main_func() 825 (ctx->shader->key.ge.as_es || ctx->stage == MESA_SHADER_GEOMETRY)) in si_llvm_translate_nir() 845 if (!ctx->shader->key.ge.as_ngg) in si_llvm_translate_nir() 851 if (shader->key.ge.as_ngg) { in si_llvm_translate_nir() 930 shader->key.ge.as_ngg && !shader->key.ge in si_llvm_translate_nir() [all...] |
H A D | si_shader.c | 65 return shader->key.ge.as_ls || shader->key.ge.as_es || in si_is_multi_part_shader() 76 return shader->key.ge.as_ngg || si_is_multi_part_shader(shader); in si_is_merged_shader() 230 return shader->key.ge.as_ngg ? 128 : 0; in si_get_max_workgroup_size() 320 if (shader->key.ge.as_ls) { in declare_vs_input_vgprs() 410 if (shader->key.ge.as_ls || stage == MESA_SHADER_TESS_CTRL) in si_init_shader_args() 412 else if (shader->key.ge.as_es || shader->key.ge.as_ngg || stage == MESA_SHADER_GEOMETRY) in si_init_shader_args() 443 if (shader->key.ge.as_es) { in si_init_shader_args() 445 } else if (shader->key.ge in si_init_shader_args() [all...] |
/third_party/lame/libmp3lame/i386/ |
H A D | nasm.h | 219 times (1 & ge4(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) jmp short %%skip 220 times (((($$-%%here) & 15)-2) & ge4(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) nop 226 times (1 & ge1(($$-%%here) & 15) & ~ge2(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) nop 227 times (1 & ge2(($$-%%here) & 15) & ~ge3(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) DB 08Bh,0C0h 228 times (1 & ge3(($$-%%here) & 15) & ~ge4(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) DB 08Dh,004h,020h 229 times (1 & ge4(($$-%%here) & 15) & ~ge5(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) DB 08Dh,044h,020h,000h 230 times (1 & ge5(($$-%%here) & 15) & ~ge6(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) DB 08Dh,044h,020h,000h,090h 231 times (1 & ge6(($$-%%here) & 15) & ~ge7(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) DB 08Dh,080h,0,0,0,0 232 times (1 & ge7(($$-%%here) & 15) & ~ge8(($$-%%here) & 15) & ~ge%1(($$-%%here) & 15)) DB 08Dh,004h,005h,0,0,0,0 233 times (1 & ge8(($$-%%here) & 15) & ~ge9(($$-%%here) & 15) & ~ge [all...] |