| /third_party/vixl/test/aarch64/ |
| H A D | test-cpu-features-aarch64.cc | 3358 TEST_FP_NEON(frsqrts_0, frsqrts(v0.V2S(), v1.V2S(), v2.V2S()))
3359 TEST_FP_NEON(frsqrts_1, frsqrts(v0.V4S(), v1.V4S(), v2.V4S()))
3360 TEST_FP_NEON(frsqrts_2, frsqrts(v0.V2D(), v1.V2D(), v2.V2D()))
3361 TEST_FP_NEON(frsqrts_3, frsqrts(s0, s1, s2))
3362 TEST_FP_NEON(frsqrts_4, frsqrts(d0, d1, d2))
3725 TEST_FP_NEON_NEONHALF(frsqrts_0, frsqrts(v0.V4H(), v1.V4H(), v2.V4H()))
3726 TEST_FP_NEON_NEONHALF(frsqrts_1, frsqrts(v0.V8H(), v1.V8H(), v2.V8H()))
3727 TEST_FP_NEON_NEONHALF(frsqrts_2, frsqrts(h0, h1, h2))
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| H A D | test-trace-aarch64.cc | 586 __ frsqrts(d4, d29, d17); in GenerateTestSequenceFP()
587 __ frsqrts(s14, s3, s24); in GenerateTestSequenceFP()
2729 __ frsqrts(v25.V2D(), v28.V2D(), v15.V2D()); in GenerateTestSequenceNEONFP()
2730 __ frsqrts(v9.V2S(), v26.V2S(), v10.V2S()); in GenerateTestSequenceNEONFP()
2731 __ frsqrts(v5.V4S(), v1.V4S(), v10.V4S()); in GenerateTestSequenceNEONFP()
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| H A D | test-simulator-aarch64.cc | 4634 DEFINE_TEST_NEON_3SAME_FP(frsqrts, Basic)
4696 DEFINE_TEST_NEON_3SAME_FP_SCALAR(frsqrts, Basic)
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| H A D | test-disasm-sve-aarch64.cc | 1265 COMPARE(frsqrts(z5.VnH(), z6.VnH(), z28.VnH()), "frsqrts z5.h, z6.h, z28.h"); in TEST()
1266 COMPARE(frsqrts(z5.VnS(), z6.VnS(), z28.VnS()), "frsqrts z5.s, z6.s, z28.s"); in TEST()
1267 COMPARE(frsqrts(z5.VnD(), z6.VnD(), z28.VnD()), "frsqrts z5.d, z6.d, z28.d"); in TEST()
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| H A D | test-api-movprfx-aarch64.cc | 635 __ frsqrts(z29.VnH(), z5.VnH(), z20.VnH()); in TEST()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 2080 LogicVRegister frsqrts(VectorFormat vform, LogicVRegister dst,
2083 LogicVRegister frsqrts(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-logic-arm64.cc | 3312 LogicVRegister Simulator::frsqrts(VectorFormat vform, LogicVRegister dst, in frsqrts() function in v8::internal::Simulator
3384 LogicVRegister Simulator::frsqrts(VectorFormat vform, LogicVRegister dst, in frsqrts() function in v8::internal::Simulator
3388 frsqrts<float>(vform, dst, src1, src2); in frsqrts()
3391 frsqrts<double>(vform, dst, src1, src2); in frsqrts()
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| H A D | simulator-arm64.cc | 4266 frsqrts(vf, rd, rn, rm);
5530 frsqrts(vf, rd, rn, rm);
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| /third_party/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 5079 LogicVRegister Simulator::frsqrts(VectorFormat vform,
5094 LogicVRegister Simulator::frsqrts(VectorFormat vform,
5099 frsqrts<SimFloat16>(vform, dst, src1, src2);
5101 frsqrts<float>(vform, dst, src1, src2);
5104 frsqrts<double>(vform, dst, src1, src2);
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| H A D | simulator-aarch64.h | 4530 LogicVRegister frsqrts(VectorFormat vform,
4534 LogicVRegister frsqrts(VectorFormat vform,
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| H A D | simulator-aarch64.cc | 7420 frsqrts(vf, rd, rn, rm); in Simulator()
7624 SIM_FUNC(FRSQRTS, frsqrts); in Simulator()
9013 frsqrts(vf, rd, rn, rm); in Simulator()
9126 frsqrts(kFormatH, rd, rn, rm); in Simulator()
10331 frsqrts(vform, zd, zn, zm); in Simulator()
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| H A D | assembler-aarch64.h | 3300 void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm);
4473 void frsqrts(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
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| H A D | macro-assembler-aarch64.h | 2885 V(frsqrts, Frsqrts) \
4845 frsqrts(zd, zn, zm); in Frsqrts()
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| H A D | assembler-aarch64.cc | 4232 V(frsqrts, NEON_FRSQRTS, NEON_FRSQRTS_scalar, NEON_FRSQRTS_H_scalar) \
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| H A D | assembler-sve-aarch64.cc | 1005 void Assembler::frsqrts(const ZRegister& zd, in frsqrts() function in vixl::aarch64::Assembler
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1429 void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 387 V(frsqrts, Frsqrts) \
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| H A D | assembler-arm64.cc | 3132 V(frsqrts, NEON_FRSQRTS, NEON_FRSQRTS_scalar) \
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