Searched refs:fcvtxn (Results 1 - 15 of 15) sorted by relevance
/third_party/vixl/test/aarch64/ |
H A D | test-simulator-aarch64.cc | 4883 DEFINE_TEST_NEON_2DIFF_FP_NARROW_2S(fcvtxn, Conversions) 4934 CALL_TEST_NEON_HELPER_2DIFF(fcvtxn, S, D, kInputDoubleConversions); in TEST()
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H A D | test-trace-aarch64.cc | 505 __ fcvtxn(s12, d12); in GenerateTestSequenceFP() 2606 __ fcvtxn(v29.V2S(), v11.V2D()); in GenerateTestSequenceNEONFP()
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H A D | test-cpu-features-aarch64.cc | 3220 TEST_FP_NEON(fcvtxn_0, fcvtxn(v0.V2S(), v1.V2D())) 3222 TEST_FP_NEON(fcvtxn_1, fcvtxn(s0, d1))
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/third_party/node/deps/v8/src/codegen/arm64/ |
H A D | assembler-arm64.h | 1721 void fcvtxn(const VRegister& vd, const VRegister& vn);
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H A D | macro-assembler-arm64.h | 1588 fcvtxn(vd, vn); in Fcvtxn()
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H A D | assembler-arm64.cc | 2774 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) { in fcvtxn() function in v8::internal::Assembler
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/third_party/vixl/src/aarch64/ |
H A D | simulator-aarch64.cc | 2424 fcvtxn(kFormatVnS, result, zn); in Simulator() 2428 fcvtxn(kFormatVnS, result, zn); in Simulator() 7078 fcvtxn(vf_fcvtn, rd, rn); in Simulator() 8861 // Unlike all of the other FP instructions above, fcvtxn encodes dest in Simulator() 8864 fcvtxn(kFormatS, rd, rn); in Simulator()
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H A D | simulator-aarch64.h | 4705 LogicVRegister fcvtxn(VectorFormat vform,
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H A D | assembler-aarch64.h | 2407 void fcvtxn(const VRegister& vd, const VRegister& vn);
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H A D | assembler-aarch64.cc | 3614 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) {
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H A D | logic-aarch64.cc | 6052 LogicVRegister Simulator::fcvtxn(VectorFormat vform,
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H A D | macro-assembler-aarch64.h | 1550 fcvtxn(vd, vn); in Fcvtxn()
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/third_party/node/deps/v8/src/execution/arm64/ |
H A D | simulator-arm64.h | 2146 LogicVRegister fcvtxn(VectorFormat vform, LogicVRegister dst,
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H A D | simulator-arm64.cc | 4047 fcvtxn(vf_fcvtn, rd, rn); 5452 // Unlike all of the other FP instructions above, fcvtxn encodes dest 5455 fcvtxn(kFormatS, rd, rn);
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H A D | simulator-logic-arm64.cc | 3859 LogicVRegister Simulator::fcvtxn(VectorFormat vform, LogicVRegister dst, in fcvtxn() function in v8::internal::Simulator
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