Searched refs:faddv (Results 1 - 7 of 7) sorted by relevance
| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 4817 LogicVRegister faddv(VectorFormat vform,
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| H A D | assembler-aarch64.h | 4141 void faddv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
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| H A D | assembler-sve-aarch64.cc | 1326 void Assembler::faddv(const VRegister& vd, in faddv() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 5625 LogicVRegister Simulator::faddv(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 4360 faddv(vd, pg, zn); in Faddv()
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| H A D | simulator-aarch64.cc | 10528 fn = &Simulator::faddv; in Simulator()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-sve-aarch64.cc | 1542 COMPARE(faddv(h26, p6, z16.VnH()), "faddv h26, p6, z16.h"); in TEST()
1543 COMPARE(faddv(s26, p6, z16.VnS()), "faddv s26, p6, z16.s"); in TEST()
1544 COMPARE(faddv(d26, p6, z16.VnD()), "faddv d26, p6, z16.d"); in TEST()
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