Searched refs:enabled_rb_mask (Results 1 - 10 of 10) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_query.c | 85 * if (enabled_rb_mask & (1 << i)) { in build_occlusion_query_shader()
115 unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask; in build_occlusion_query_shader() local
140 nir_iand_imm(&b, nir_ishl(&b, nir_imm_int(&b, 1), current_outer_count), enabled_rb_mask); in build_occlusion_query_shader()
1229 uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask; in radv_GetQueryPoolResults() local
1236 if (!(enabled_rb_mask & (1 << i))) in radv_GetQueryPoolResults()
1521 unsigned enabled_rb_mask = cmd_buffer->device->physical_device->rad_info.enabled_rb_mask; in radv_CmdCopyQueryPoolResults() local
1522 uint32_t rb_avail_offset = 16 * util_last_bit(enabled_rb_mask) in radv_CmdCopyQueryPoolResults()
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| H A D | si_cmd_buffer.c | 179 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask; in si_set_raster_config()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | r600_query.c | 541 unsigned enabled_rb_mask = rscreen->info.enabled_rb_mask; in r600_query_hw_prepare_buffer() local
549 if (!(enabled_rb_mask & (1<<i))) { in r600_query_hw_prepare_buffer()
1829 /* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
1881 rscreen->info.enabled_rb_mask = mask; in r600_query_fix_enabled_rb_mask()
1924 mask != rscreen->info.enabled_rb_mask) { in r600_query_fix_enabled_rb_mask()
1925 printf("enabled_rb_mask (fixed) = 0x%x\n", mask); in r600_query_fix_enabled_rb_mask()
1927 rscreen->info.enabled_rb_mask = mask; in r600_query_fix_enabled_rb_mask()
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| H A D | r600_pipe_common.c | 1325 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask); in r600_common_screen_init()
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| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_gpu_info.h | 229 uint32_t enabled_rb_mask; /* GCN harvest config */ member
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| H A D | ac_gpu_info.c | 1195 info->enabled_rb_mask = amdinfo.enabled_rb_pipes_mask; in ac_query_gpu_info()
1297 util_bitcount(info->enabled_rb_mask) != in ac_query_gpu_info()
1333 info->num_rb = util_bitcount(info->enabled_rb_mask); in ac_query_gpu_info()
1579 fprintf(f, " enabled_rb_mask = 0x%x\n", info->enabled_rb_mask); in ac_print_gpu_info()
1755 unsigned rb_mask = info->enabled_rb_mask; in ac_get_harvested_configs()
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| H A D | ac_surface.c | 523 regValue.backendDisables = info->enabled_rb_mask; in ac_addrlib_create()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_winsys.c | 438 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.max_render_backends); in do_winsys_init()
441 * default enabled_rb_mask with the result of the last query. in do_winsys_init()
445 &ws->info.enabled_rb_mask); in do_winsys_init()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_query.c | 620 unsigned enabled_rb_mask = screen->info.enabled_rb_mask; in si_query_hw_prepare_buffer() local
628 if (!(enabled_rb_mask & (1 << i))) { in si_query_hw_prepare_buffer()
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| H A D | si_state.c | 2436 const unsigned max_eqaa_samples = util_bitcount(sscreen->info.enabled_rb_mask) <= 1 ? 8 : 16; in si_is_format_supported()
5524 unsigned rb_mask = sscreen->info.enabled_rb_mask; in si_set_raster_config()
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