| /third_party/libunwind/libunwind/src/ia64/ |
| H A D | Grbs.c | 203 unw_word_t n, src_mask, dst_mask, bsp, *dst, src_rnat, dst_rnat = 0; in rbs_cover_and_flush() local
290 dst_mask = ((unw_word_t) 1) << rse_slot_num ((unw_word_t) dst); in rbs_cover_and_flush()
293 dst_rnat |= dst_mask; in rbs_cover_and_flush()
295 dst_rnat &= ~dst_mask; in rbs_cover_and_flush()
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| /third_party/mesa3d/src/amd/vulkan/radix_sort/common/vk/ |
| H A D | barrier.c | 238 VkAccessFlags dst_mask) in vk_memory_barrier()
243 .dstAccessMask = dst_mask }; in vk_memory_barrier()
234 vk_memory_barrier(VkCommandBuffer cb, VkPipelineStageFlags src_stage, VkAccessFlags src_mask, VkPipelineStageFlags dst_stage, VkAccessFlags dst_mask) vk_memory_barrier() argument
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| H A D | barrier.h | 55 VkAccessFlags dst_mask);
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| /third_party/mesa3d/src/gallium/auxiliary/util/ |
| H A D | u_surface.c | 503 uint32_t dst_mask; in util_fill_zs_rect() local
505 dst_mask = 0x00ffffff; in util_fill_zs_rect()
508 dst_mask = 0xffffff00; in util_fill_zs_rect()
511 dst_mask = ~dst_mask; in util_fill_zs_rect()
515 uint32_t tmp = *row & dst_mask; in util_fill_zs_rect()
516 *row++ = tmp | ((uint32_t) zstencil & ~dst_mask); in util_fill_zs_rect()
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_compiler_util.h | 83 unsigned int dst_mask);
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| H A D | radeon_dataflow.c | 685 unsigned int dst_mask) in get_readers_for_single_write()
702 d->DstMask = dst_mask; in get_readers_for_single_write()
703 d->AliveWriteMask = dst_mask; in get_readers_for_single_write()
706 if (!dst_mask) in get_readers_for_single_write()
680 get_readers_for_single_write( void * userdata, struct rc_instruction * writer, rc_register_file dst_file, unsigned int dst_index, unsigned int dst_mask) get_readers_for_single_write() argument
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| H A D | radeon_compiler_util.c | 325 unsigned int dst_mask) in rc_src_reads_dst_mask()
330 return dst_mask & rc_swizzle_to_writemask(src_swz); in rc_src_reads_dst_mask()
319 rc_src_reads_dst_mask( rc_register_file src_file, unsigned int src_idx, unsigned int src_swz, rc_register_file dst_file, unsigned int dst_idx, unsigned int dst_mask) rc_src_reads_dst_mask() argument
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| /third_party/mesa3d/src/broadcom/vulkan/ |
| H A D | v3dv_cmd_buffer.c | 567 if (!(cmd_buffer->state.barrier.dst_mask & V3DV_BARRIER_GRAPHICS_BIT)) { in v3dv_cmd_buffer_finish_job()
655 uint8_t barrier_mask = cmd_buffer->state.barrier.dst_mask; in cmd_buffer_serialize_job_if_needed()
681 cmd_buffer->state.barrier.dst_mask &= ~bit; in cmd_buffer_serialize_job_if_needed()
1655 dst->dst_mask |= src->dst_mask; in v3dv_cmd_buffer_merge_barrier_state()
1698 if (pending_barrier.dst_mask) { in cmd_buffer_execute_outside_pass()
1717 assert(secondary->state.barrier.dst_mask || in cmd_buffer_execute_outside_pass()
1723 if (pending_barrier.dst_mask) { in cmd_buffer_execute_outside_pass()
2829 cmd_buffer->state.barrier.dst_mask |= V3DV_BARRIER_COMPUTE_BIT; in v3dv_CmdPipelineBarrier()
2835 cmd_buffer->state.barrier.dst_mask | in v3dv_CmdPipelineBarrier()
[all...] |
| H A D | v3dvx_cmd_buffer.c | 1682 pending_barrier.dst_mask) { in cmd_buffer_execute_inside_pass()
1727 if (pending_barrier.dst_mask) { in cmd_buffer_execute_inside_pass()
1753 assert(secondary->state.barrier.dst_mask || in cmd_buffer_execute_inside_pass()
1760 if (pending_barrier.dst_mask) { in cmd_buffer_execute_inside_pass()
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| H A D | v3dv_private.h | 1254 uint8_t dst_mask; member
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| H A D | v3dv_queue.c | 1106 if (cmd_buffer->state.barrier.dst_mask) { in v3dv_queue_driver_submit()
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| /third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
| H A D | lp_bld_format_aos.c | 165 LLVMValueRef dst_mask; in scale_bits_up() local
167 dst_mask = lp_build_const_int_vec(gallivm, src_type, in scale_bits_up()
171 result = lp_build_andnot(&bld, dst_mask, result); in scale_bits_up()
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| /third_party/mesa3d/src/intel/vulkan/ |
| H A D | anv_blorp.c | 338 dst_mask = region->dstSubresource.aspectMask; in copy_image() local
340 assert(anv_image_aspects_compatible(src_mask, dst_mask)); in copy_image()
388 get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, dst_mask, in copy_image()
392 anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image, dst_mask, in copy_image()
406 dst_image, dst_mask, in copy_image()
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_lowering.c | 113 aliases(const struct tgsi_full_dst_register *dst, unsigned dst_mask, in aliases() argument
124 if (actual_mask & dst_mask) in aliases()
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| /third_party/mesa3d/src/freedreno/vulkan/ |
| H A D | tu_cmd_buffer.c | 2977 enum tu_cmd_access_mask dst_mask) in tu_flush_for_access()
3020 if (dst_mask & (TU_ACCESS_SYSMEM_READ | TU_ACCESS_SYSMEM_WRITE)) { in tu_flush_for_access()
3025 if (dst_mask & (TU_ACCESS_##domain##_READ | \ in tu_flush_for_access()
3039 if (dst_mask & (TU_ACCESS_##domain##_INCOHERENT_READ | \ in tu_flush_for_access()
2975 tu_flush_for_access(struct tu_cache_state *cache, enum tu_cmd_access_mask src_mask, enum tu_cmd_access_mask dst_mask) tu_flush_for_access() argument
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