| /third_party/optimized-routines/string/aarch64/ |
| H A D | strncmp-mte.S | 80 csinv endloop, diff, xzr, hi /* Last Dword or differences. */
171 csinv limit, limit, xzr, lo
251 csinv endloop, diff, xzr, hi /* If limit, set to all ones. */
279 csinv tmp3, syndrome, xzr, hi /* If limit, set to all ones. */
289 csinv tmp3, syndrome, xzr, hi /* If limit, set to all ones. */
|
| H A D | strcpy.S | 266 csinv data1, data1, xzr, lt
|
| H A D | strncmp.S | 70 csinv endloop, diff, xzr, pl /* Last Dword or differences. */
|
| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 2249 COMPARE(csinv(w12, w13, w14, mi), "csinv w12, w13, w14, mi"); in TEST()
2250 COMPARE(csinv(x15, x16, x17, pl), "csinv x15, x16, x17, pl"); in TEST()
2268 COMPARE(csinv(x4, x5, x6, al), "csinv x4, x5, x6, al"); in TEST()
2269 COMPARE(csinv(x5, x6, x7, nv), "csinv x5, x6, x7, nv"); in TEST()
2286 COMPARE_MACRO(Csel(w0, w1, -1, eq), "csinv w0, w1, wzr, eq"); in TEST()
2310 COMPARE_MACRO(Csel(x6, x7, -1, lo), "csinv x in TEST()
[all...] |
| H A D | test-trace-aarch64.cc | 133 __ csinv(w29, w2, w3, eq); in GenerateTestSequenceBase()
134 __ csinv(w29, w2, w3, ne); in GenerateTestSequenceBase()
135 __ csinv(x4, x5, x6, cc); in GenerateTestSequenceBase()
136 __ csinv(x4, x5, x6, cs); in GenerateTestSequenceBase()
|
| H A D | test-cpu-features-aarch64.cc | 258 TEST_NONE(csinv_0, csinv(w0, w1, w2, cc))
259 TEST_NONE(csinv_1, csinv(x0, x1, x2, ne))
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 483 csinv(rd, rn, rm, cond); in Csinv()
|
| H A D | assembler-arm64.cc | 1025 void Assembler::csinv(const Register& rd, const Register& rn, in csinv() function in v8::internal::Assembler
1044 csinv(rd, zr, zr, NegateCondition(cond)); in csetm()
1054 csinv(rd, rn, rn, NegateCondition(cond)); in cinv()
|
| H A D | assembler-arm64.h | 696 void csinv(const Register& rd, const Register& rn, const Register& rm,
|
| H A D | macro-assembler-arm64.cc | 674 csinv(rd, rn, zr, cond); in Csel()
|
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 741 void Assembler::csinv(const Register& rd, in csinv() function in vixl::aarch64::Assembler
767 csinv(rd, zr, zr, InvertCondition(cond)); in csetm()
779 csinv(rd, rn, rn, InvertCondition(cond)); in cinv()
|
| H A D | macro-assembler-aarch64.cc | 1481 masm->csinv(rd, left_register, zr, cond); in Emit()
|
| H A D | assembler-aarch64.h | 917 void csinv(const Register& rd,
|
| H A D | macro-assembler-aarch64.h | 1447 csinv(rd, rn, rm, cond); in Csinv()
|