| /third_party/lwip/src/core/ipv6/ |
| H A D | ip6_frag.c | 752 u16_t left, cop; in ip6_frag() local
771 cop = last ? left : nfb; in ip6_frag()
774 rambuf = pbuf_alloc(PBUF_IP, cop + IP6_FRAG_HLEN, PBUF_RAM); in ip6_frag()
781 poff += pbuf_copy_partial(p, (u8_t*)rambuf->payload + IP6_FRAG_HLEN, cop, poff); in ip6_frag()
814 left_to_copy = cop; in ip6_frag()
860 IP6H_PLEN_SET(ip6hdr, (u16_t)(cop + IP6_FRAG_HLEN)); in ip6_frag()
876 left = (u16_t)(left - cop); in ip6_frag()
877 fragment_offset = (u16_t)(fragment_offset + cop); in ip6_frag()
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| /third_party/python/Modules/_decimal/tests/ |
| H A D | deccheck.py | 361 self.cop = RestrictedList() # converted C.Decimal operands
544 if t.cop[0].is_nan() and t.pop[0].is_nan():
581 cargs = t.cop
588 cself, cargs = t.cop[0], t.cop[1:]
692 t.cop.append(op)
722 t.cop.append(c)
747 t.cop.append(op.c)
752 t.cop.append(op)
760 t.cop an
[all...] |
| /third_party/skia/third_party/externals/spirv-cross/ |
| H A D | spirv_cross_parsed_ir.cpp | 519 auto &cop = get<SPIRConstantOp>(id); in mark_used_as_array_length() local
520 if (cop.opcode == OpCompositeExtract) in mark_used_as_array_length()
521 mark_used_as_array_length(cop.arguments[0]); in mark_used_as_array_length()
522 else if (cop.opcode == OpCompositeInsert) in mark_used_as_array_length()
524 mark_used_as_array_length(cop.arguments[0]); in mark_used_as_array_length()
525 mark_used_as_array_length(cop.arguments[1]); in mark_used_as_array_length()
528 for (uint32_t arg_id : cop.arguments) in mark_used_as_array_length()
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| H A D | spirv_glsl.cpp | 4653 string CompilerGLSL::constant_op_expression(const SPIRConstantOp &cop)
4655 auto &type = get<SPIRType>(cop.basetype);
4660 if (is_legacy() && is_unsigned_opcode(cop.opcode))
4664 switch (cop.opcode)
4717 if (cop.arguments.size() < 3)
4725 if (to_trivial_mix_op(type, op, cop.arguments[2], cop.arguments[1], cop.arguments[0]))
4732 return to_ternary_expression(type, cop.arguments[0], cop
[all...] |
| H A D | spirv_glsl.hpp | 389 std::string constant_op_expression(const SPIRConstantOp &cop);
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| /third_party/mesa3d/src/imagination/vulkan/pds/ |
| H A D | pvr_rogue_pds_encode.h | 279 uint32_t cop, in pvr_pds_inst_encode_cmp()
294 ((cop & PVR_ROGUE_PDSINST_COP_MASK) << PVR_ROGUE_PDSINST_CMP_COP_SHIFT); in pvr_pds_inst_encode_cmp()
303 uint32_t cop, in pvr_pds_inst_encode_cmpi()
318 ((cop & PVR_ROGUE_PDSINST_COP_MASK) << PVR_ROGUE_PDSINST_CMPI_COP_SHIFT); in pvr_pds_inst_encode_cmpi()
278 pvr_pds_inst_encode_cmp(uint32_t cc, uint32_t cop, uint32_t src0, uint32_t src1) pvr_pds_inst_encode_cmp() argument
302 pvr_pds_inst_encode_cmpi(uint32_t cc, uint32_t cop, uint32_t src0, uint32_t im16) pvr_pds_inst_encode_cmpi() argument
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| H A D | pvr_rogue_pds_disasm.h | 248 enum pvr_cop cop; member
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| H A D | pvr_pds_printer.c | 298 COP[cmp->cop], in pvr_pds_disassemble_instruction_cmp()
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| H A D | pvr_pds_disasm.c | 555 cmp->cop = instruction >> PVR_ROGUE_PDSINST_CMP_COP_SHIFT & in pvr_pds_disassemble_instruction_cmp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 266 auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
749 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
811 RegisterCell R2 = cop(2, W0);
812 RegisterCell R3 = cop(3, W0);
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| /third_party/mksh/ |
| H A D | exec.c | 1775 pr_list(struct columnise_opts *cop, char * const *ap) in pr_list() argument
1790 print_columns(cop, n, plain_fmt_entry, (const void *)ap, in pr_list()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 5845 unsigned cop = fieldFromInstruction(Val, 8, 4); in DecoderForMRRC2AndMCRR2() local
5849 if ((cop & ~0x1) == 0xa) in DecoderForMRRC2AndMCRR2()
5862 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] in DecoderForMRRC2AndMCRR2()
5863 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] in DecoderForMRRC2AndMCRR2()
5871 Inst.addOperand(MCOperand::createImm(cop)); in DecoderForMRRC2AndMCRR2()
|