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Searched refs:clear_mask (Results 1 - 15 of 15) sorted by relevance

/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_pass.c520 (att->load || att->load_stencil) && !att->clear_mask && !att->will_be_resolved; in tu_render_pass_cond_config()
522 (att->store || att->store_stencil) && !att->clear_mask; in tu_render_pass_cond_config()
654 if (att->clear_mask) in tu_render_pass_bandwidth_config()
681 att->clear_mask = in attachment_set_ops()
692 if (att->clear_mask) in attachment_set_ops()
693 att->clear_mask = VK_IMAGE_ASPECT_DEPTH_BIT; in attachment_set_ops()
695 att->clear_mask |= VK_IMAGE_ASPECT_STENCIL_BIT; in attachment_set_ops()
702 att->clear_mask = stencil_clear ? VK_IMAGE_ASPECT_COLOR_BIT : 0; in attachment_set_ops()
707 if (att->clear_mask) in attachment_set_ops()
708 att->clear_mask in attachment_set_ops()
[all...]
H A Dtu_pass.h78 VkImageAspectFlags clear_mask; member
H A Dtu_lrz.c196 bool clears_depth = att->clear_mask & in tu_lrz_init_state()
284 if (att->clear_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_DEPTH_BIT)) { in tu_lrz_begin_resumed_renderpass()
H A Dtu_clear_blit.c2682 uint8_t clear_mask, in clear_gmem_attachment()
2689 tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO(.gmem = 1, .clear_mask = clear_mask)); in clear_gmem_attachment()
2843 VkImageAspectFlags clear_mask, in clear_sysmem_attachment()
2858 ops->setup(cmd, cs, format, format, clear_mask, 0, true, iview->view.ubwc_enabled, in clear_sysmem_attachment()
2893 if (!attachment->clear_mask) in tu_clear_sysmem_attachment()
2897 if (attachment->clear_mask & VK_IMAGE_ASPECT_DEPTH_BIT) { in tu_clear_sysmem_attachment()
2901 if (attachment->clear_mask & VK_IMAGE_ASPECT_STENCIL_BIT) { in tu_clear_sysmem_attachment()
2906 clear_sysmem_attachment(cmd, cs, attachment->format, attachment->clear_mask, in tu_clear_sysmem_attachment()
2941 if (!attachment->clear_mask) in tu_clear_gmem_attachment()
2679 clear_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum pipe_format format, uint8_t clear_mask, uint32_t gmem_offset, const VkClearValue *value) clear_gmem_attachment() argument
2840 clear_sysmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, VkFormat vk_format, VkImageAspectFlags clear_mask, const VkClearValue *value, uint32_t a, bool separate_ds) clear_sysmem_attachment() argument
[all...]
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_rast.c190 uint32_t clear_mask = (uint32_t) clear_mask64; in lp_rast_clear_zstencil() local
196 __FUNCTION__, clear_value, clear_mask); in lp_rast_clear_zstencil()
209 clear_value &= clear_mask; in lp_rast_clear_zstencil()
216 assert(clear_mask == 0xff); in lp_rast_clear_zstencil()
224 if (clear_mask == 0xffff) { in lp_rast_clear_zstencil()
236 uint16_t tmp = ~clear_mask & *row; in lp_rast_clear_zstencil()
244 if (clear_mask == 0xffffffff) { in lp_rast_clear_zstencil()
254 uint32_t tmp = ~clear_mask & *row; in lp_rast_clear_zstencil()
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dfd2_draw.c578 uint32_t clear_mask, depth_clear; variable
581 clear_mask = ((buffers & PIPE_CLEAR_DEPTH) ? 0xe : 0) |
587 clear_mask = 0xf;
598 A2XX_RB_COPY_CONTROL_CLEAR_MASK(clear_mask));
/third_party/mesa3d/src/amd/common/
H A Dac_shader_util.h134 void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask,
H A Dac_shader_util.c792 void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask, in ac_set_reg_cu_en() argument
797 uint32_t cu_en_mask = ~clear_mask; in ac_set_reg_cu_en()
/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
H A Dnv50_state.c1088 unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots); in nv50_set_vertex_buffers() local
1089 nv50->vbo_user &= clear_mask; in nv50_set_vertex_buffers()
1090 nv50->vbo_constant &= clear_mask; in nv50_set_vertex_buffers()
1091 nv50->vtxbufs_coherent &= clear_mask; in nv50_set_vertex_buffers()
1094 clear_mask = ~u_bit_consecutive(start_slot, count); in nv50_set_vertex_buffers()
1095 nv50->vbo_user &= clear_mask; in nv50_set_vertex_buffers()
1096 nv50->vbo_constant &= clear_mask; in nv50_set_vertex_buffers()
1097 nv50->vtxbufs_coherent &= clear_mask; in nv50_set_vertex_buffers()
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_state.c1032 unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots); in nvc0_set_vertex_buffers() local
1033 nvc0->vbo_user &= clear_mask; in nvc0_set_vertex_buffers()
1034 nvc0->constant_vbos &= clear_mask; in nvc0_set_vertex_buffers()
1035 nvc0->vtxbufs_coherent &= clear_mask; in nvc0_set_vertex_buffers()
1038 clear_mask = ~u_bit_consecutive(start_slot, count); in nvc0_set_vertex_buffers()
1039 nvc0->vbo_user &= clear_mask; in nvc0_set_vertex_buffers()
1040 nvc0->constant_vbos &= clear_mask; in nvc0_set_vertex_buffers()
1041 nvc0->vtxbufs_coherent &= clear_mask; in nvc0_set_vertex_buffers()
/third_party/mesa3d/src/gallium/drivers/r600/sb/
H A Dsb_valtable.cpp434 basetype clear_mask = (~(basetype)0u) << (bit_size % bt_bits);
435 data[cur_data_size - 1] &= ~clear_mask;
/third_party/mesa3d/src/imagination/vulkan/
H A Dpvr_pass.c230 load_op->clear_mask |= 1U << i; in pvr_load_op_create()
H A Dpvr_private.h1278 uint32_t clear_mask; member
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_private.h202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask) in radv_clear_mask() argument
204 if (*inout_mask & clear_mask) { in radv_clear_mask()
205 *inout_mask &= ~clear_mask; in radv_clear_mask()
/third_party/mesa3d/src/intel/vulkan/
H A Danv_private.h354 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask) in anv_clear_mask() argument
356 if (*inout_mask & clear_mask) { in anv_clear_mask()
357 *inout_mask &= ~clear_mask; in anv_clear_mask()

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