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Searched refs:bpe (Results 1 - 25 of 38) sorted by relevance

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/third_party/libdrm/radeon/
H A Dradeon_surface.c169 unsigned bpe, unsigned level, in surf_minify()
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
284 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_linear()
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear()
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear_aligned()
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
342 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_1d()
351 surf_minify(surf, surf->level+i, surf->bpe, in r6_surface_init_1d()
167 surf_minify(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, uint32_t xalign, uint32_t yalign, uint32_t zalign, uint64_t offset) surf_minify() argument
570 eg_surf_minify(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, unsigned slice_pt, unsigned mtilew, unsigned mtileh, unsigned mtileb, uint64_t offset) eg_surf_minify() argument
611 eg_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, uint64_t offset, unsigned start_level) eg_surface_init_1d() argument
652 eg_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_split, uint64_t offset, unsigned start_level) eg_surface_init_2d() argument
1421 si_surf_minify(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, uint32_t xalign, uint32_t yalign, uint32_t zalign, uint32_t slice_align, uint64_t offset) si_surf_minify() argument
1469 si_surf_minify_2d(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, unsigned slice_pt, uint32_t xalign, uint32_t yalign, uint32_t zalign, unsigned mtileb, uint64_t offset) si_surf_minify_2d() argument
1550 si_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, uint64_t offset, unsigned start_level) si_surface_init_1d() argument
1617 si_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, unsigned num_pipes, unsigned num_banks, unsigned tile_split, uint64_t offset, unsigned start_level) si_surface_init_2d() argument
1857 cik_get_2d_params(struct radeon_surface_manager *surf_man, unsigned bpe, unsigned nsamples, bool is_color, unsigned tile_mode, uint32_t *num_pipes, uint32_t *tile_split_ptr, uint32_t *num_banks, uint32_t *macro_tile_aspect, uint32_t *bank_w, uint32_t *bank_h) cik_get_2d_params() argument
2214 cik_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, unsigned tile_split, unsigned num_pipes, unsigned num_banks, uint64_t offset, unsigned start_level) cik_surface_init_2d() argument
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H A Dradeon_surface.h119 uint32_t bpe; member
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c35 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
68 unsigned bpe) in surf_level_winsys_to_drm()
74 level_drm->pitch_bytes = level_ws->nblk_x * bpe; in surf_level_winsys_to_drm()
80 unsigned bpe) in surf_level_drm_to_winsys()
87 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes); in surf_level_drm_to_winsys()
92 unsigned flags, unsigned bpe, in surf_winsys_to_drm()
108 surf_drm->bpe = bpe; in surf_winsys_to_drm()
158 bpe * surf_drm->nsamples); in surf_winsys_to_drm()
185 surf_ws->bpe in surf_drm_to_winsys()
66 surf_level_winsys_to_drm(struct radeon_surface_level *level_drm, const struct legacy_surf_level *level_ws, unsigned bpe) surf_level_winsys_to_drm() argument
78 surf_level_drm_to_winsys(struct legacy_surf_level *level_ws, const struct radeon_surface_level *level_drm, unsigned bpe) surf_level_drm_to_winsys() argument
90 surf_winsys_to_drm(struct radeon_surface *surf_drm, const struct pipe_resource *tex, unsigned flags, unsigned bpe, enum radeon_surf_mode mode, const struct radeon_surf *surf_ws) surf_winsys_to_drm() argument
345 radeon_winsys_surface_init(struct radeon_winsys *rws, const struct pipe_resource *tex, uint64_t flags, unsigned bpe, enum radeon_surf_mode mode, struct radeon_surf *surf_ws) radeon_winsys_surface_init() argument
376 unsigned fmask_flags, bpe; radeon_winsys_surface_init() local
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/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_surface.c65 uint64_t flags, unsigned bpe, in amdgpu_surface_init()
78 surf->bpe = bpe; in amdgpu_surface_init()
63 amdgpu_surface_init(struct radeon_winsys *rws, const struct pipe_resource *tex, uint64_t flags, unsigned bpe, enum radeon_surf_mode mode, struct radeon_surf *surf) amdgpu_surface_init() argument
/third_party/mesa3d/src/amd/common/
H A Dac_surface.c857 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
870 unsigned bpe = surf->bpe; in get_display_flag() local
888 (bpe >= 4 && bpe <= 8 && num_channels == 4) || in get_display_flag()
890 (bpe == 2 && num_channels >= 3) || in get_display_flag()
892 (bpe == 1 && num_channels == 1)) in get_display_flag()
1018 * blk_w, blk_h, bpe, flags.
1079 switch (surf->bpe) { in gfx6_compute_surface()
1090 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * in gfx6_compute_surface()
3247 ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info, unsigned bpe, struct gfx9_meta_equation *equation, nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height, nir_ssa_def *dcc_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *sample, nir_ssa_def *pipe_xor) ac_nir_dcc_addr_from_coord() argument
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H A Dac_surface.h311 uint8_t bpe : 5; member
481 unsigned bpe, struct gfx9_meta_equation *equation,
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_texture.c58 if (rdst->surface.bpe != rsrc->surface.bpe) in r600_prepare_for_dma_blit()
181 rtex->surface.bpe; in r600_texture_get_offset()
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
211 unsigned i, bpe, flags = 0; in r600_init_surface() local
218 bpe = 4; /* stencil is allocated separately on evergreen */ in r600_init_surface()
220 bpe = util_format_get_blocksize(ptex->format); in r600_init_surface()
221 assert(util_is_power_of_two_or_zero(bpe)); in r600_init_surface()
248 flags, bpe, array_mode, surface); in r600_init_surface()
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) { in r600_init_surface()
601 unsigned flags, bpe; r600_texture_get_fmask_info() local
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H A Dradeon_vce.c234 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in rvce_frame_offset()
455 cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in rvce_create_encoder()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c34 if (dst->surface.bpe != src->surface.bpe) in si_prepare_for_sdma_copy()
61 return util_logbase2(tex->surface.bpe) | in encode_legacy_tile_info()
115 unsigned bpp = sdst->surface.bpe; in si_sdma_v4_v5_copy_texture()
228 unsigned bpp = sdst->surface.bpe; in cik_sdma_copy_texture()
H A Dradeon_vce.c223 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); in si_vce_frame_offset()
226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); in si_vce_frame_offset()
454 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in si_vce_create_encoder()
458 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in si_vce_create_encoder()
H A Dradeon_vce_40_2_2.c85 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
86 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
315 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
316 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
H A Dradeon_uvd_enc_1_1.c760 enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); in radeon_uvd_enc_ctx()
762 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); in radeon_uvd_enc_ctx()
764 enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe; in radeon_uvd_enc_ctx()
765 enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe; in radeon_uvd_enc_ctx()
879 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); in radeon_uvd_enc_encode_params_hevc()
881 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); in radeon_uvd_enc_encode_params_hevc()
883 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe; in radeon_uvd_enc_encode_params_hevc()
885 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe; in radeon_uvd_enc_encode_params_hevc()
H A Dradeon_vce_52.c194 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
195 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
198 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch in create()
199 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch in create()
270 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
271 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
278 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch in encode()
279 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch in encode()
H A Dsi_texture.c143 *stride = pitch * tex->surface.bpe; in si_texture_get_offset()
154 tex->surface.bpe; in si_texture_get_offset()
156 *stride = tex->surface.u.legacy.level[level].nblk_x * tex->surface.bpe; in si_texture_get_offset()
169 tex->surface.bpe; in si_texture_get_offset()
181 unsigned bpe; in si_init_surface() local
188 bpe = 4; /* stencil is allocated separately */ in si_init_surface()
190 bpe = util_format_get_blocksize(ptex->format); in si_init_surface()
191 assert(util_is_power_of_two_or_zero(bpe)); in si_init_surface()
208 bpe = 4; in si_init_surface()
242 if (sscreen->info.family == CHIP_STONEY && bpe in si_init_surface()
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H A Dsi_shaderlib_nir.c170 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation, in si_create_dcc_retile_cs()
178 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, in si_create_dcc_retile_cs()
217 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, tex->surface.bpe, in gfx9_create_clear_dcc_msaa_cs()
H A Dsi_state_binning.c74 sum += tex->surface.bpe; in si_get_color_bin_size()
341 cColor += tex->surface.bpe * mmrt; in gfx10_get_bin_sizes()
H A Dradeon_vce_50.c125 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
126 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
H A Dradeon_uvd_enc.c325 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * in radeon_uvd_create_encoder()
327 : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in radeon_uvd_create_encoder()
H A Dsi_clear.c140 if (tex->surface.bpe == 16) { in si_set_clear_color()
558 switch (tex->surface.bpe) { in si_set_optimal_micro_tile_mode()
571 switch (tex->surface.bpe) { in si_set_optimal_micro_tile_mode()
767 !sctx->screen->allow_dcc_msaa_clear_to_reg_for_bpp[util_logbase2(tex->surface.bpe)]) in si_fast_clear()
808 if (tex->surface.bpe > 8) { in si_fast_clear()
/third_party/mesa3d/src/amd/addrlib/src/core/
H A Daddrlib2.cpp903 else if ((pIn->bpe != 0) && in ComputeSlicePipeBankXor()
904 (pIn->bpe != 8) && in ComputeSlicePipeBankXor()
905 (pIn->bpe != 16) && in ComputeSlicePipeBankXor()
906 (pIn->bpe != 32) && in ComputeSlicePipeBankXor()
907 (pIn->bpe != 64) && in ComputeSlicePipeBankXor()
908 (pIn->bpe != 128)) in ComputeSlicePipeBankXor()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_image.c1401 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; in radv_init_metadata()
1419 if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 || image->info.levels > 1 || in radv_image_alloc_single_sample_cmask()
1625 image->planes[i].surface.bpe = vk_format_get_blocksize(format); in radv_image_reset_layout()
1628 if (image->planes[i].surface.bpe == 3) { in radv_image_reset_layout()
1629 image->planes[i].surface.bpe = 4; in radv_image_reset_layout()
1685 if (mod_info->pPlaneLayouts[plane].rowPitch % image->planes[plane].surface.bpe || in radv_image_create_layout()
1690 stride = mod_info->pPlaneLayouts[plane].rowPitch / image->planes[plane].surface.bpe; in radv_image_create_layout()
2439 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3; in radv_GetImageSubresourceLayout()
2444 assert(util_is_power_of_two_nonzero(surface->bpe)); in radv_GetImageSubresourceLayout()
2445 pLayout->rowPitch = pitch * surface->bpe; in radv_GetImageSubresourceLayout()
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H A Dradv_meta_dcc_retile.c63 nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe, in build_dcc_retile_compute_shader()
68 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, in build_dcc_retile_compute_shader()
H A Dradv_sdma_copy_image.c77 unsigned bpp = image->planes[0].surface.bpe; in radv_sdma_v4_v5_copy_image_to_buffer()
/third_party/python/Lib/concurrent/futures/
H A Dprocess.py481 bpe = BrokenProcessPool("A process in the process pool was "
485 bpe.__cause__ = _RemoteTraceback(
490 work_item.future.set_exception(bpe)
/third_party/mesa3d/src/amd/addrlib/src/
H A Daddrinterface.cpp867 UINT_32 bpe = 0; in ElemSize() local
873 bpe = pLib->GetBpe(format); in ElemSize()
876 return bpe; in ElemSize()

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