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Searched refs:banks (Results 1 - 12 of 12) sorted by relevance

/third_party/mesa3d/src/amd/addrlib/src/r800/
H A Degbaddrlib.cpp945 macroTileHeight = MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks / in ComputeSurfaceAlignmentsMacroTiled()
955 pipes * pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize; in ComputeSurfaceAlignmentsMacroTiled()
980 switch (pTileInfo->banks) in SanityCheckMacroTiled()
1040 if (pTileInfo->banks < pTileInfo->macroAspectRatio) in SanityCheckMacroTiled()
1063 ADDR_ASSERT(numPipes * pTileInfo->banks >= 4); in SanityCheckMacroTiled()
1494 (MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks) /
1641 UINT_32 numBankBits = Log2(pTileInfo->banks);
1735 (MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks) / pTileInfo->macroAspectRatio;
1743 (numPipes * pTileInfo->banks);
2352 UINT_32 banks
[all...]
H A Dciaddrlib.cpp241 pOut->dccRamBaseAlign = pIn->tileInfo.banks * in HwlComputeDccInfo()
299 UINT_32 numOfBanks = pIn->pTileInfo->banks; in HwlComputeCmaskAddrFromCoord()
343 UINT_32 numOfBanks = pIn->pTileInfo->banks; in HwlComputeHtileAddrFromCoord()
611 pInfo->banks = 2; in HwlSetupTileCfg()
966 tileInfo.banks * tileInfo.bankWidth * in HwlOptimizeTileMode()
1490 HwlGetPipes(&tileInfo) * tileInfo.banks * in HwlSetupTileInfo()
1501 HwlGetPipes(&tileInfo) * tileInfo.banks * in HwlSetupTileInfo()
1645 pCfg->info.banks = 2; in ReadGbTileMode()
1741 pCfg->banks = 1 << (gbTileMode.f.alt_num_banks + 1); in ReadGbMacroTileCfg()
1747 pCfg->banks in ReadGbMacroTileCfg()
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H A Dsiaddrlib.cpp247 switch (pTileInfo->banks) in ComputeBankEquation()
2523 UINT_32 yBitToCheck = QLog2(pTileInfo->banks) - 1; in HwlComputeSurfaceCoord2DFromBankPipe()
3019 pInfo->banks = 2;
3083 pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1);
3527 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks *
3655 key.fields.numBanksLog2 = Log2(tileConfig.info.banks);
3721 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
3800 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
/third_party/pulseaudio/speex/libspeexdsp/
H A Dfilterbank.c54 FilterBank *filterbank_new(int banks, spx_word32_t sampling, int len, int type) in filterbank_new() argument
64 mel_interval = PDIV32(max_mel,banks-1); in filterbank_new()
67 bank->nb_banks = banks; in filterbank_new()
75 bank->scaling = (float*)speex_alloc(banks*sizeof(float)); in filterbank_new()
91 if (id1>banks-2) in filterbank_new()
93 id1 = banks-2; in filterbank_new()
H A Dfilterbank.h52 FilterBank *filterbank_new(int banks, spx_word32_t sampling, int len, int type);
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs_bank_conflicts.cpp274 * atoms are assigned the same bank b or opposite-parity banks b and b^1).
674 * incur a conflict iff they are assigned opposite banks (b and in shader_conflict_weight_matrix()
819 weight_vector_type *banks = new weight_vector_type[4]; in bank_characteristics() local
822 banks[b] = weight_vector_type(2 * map.size); in bank_characteristics()
826 set(banks[b], j, p, in bank_characteristics()
831 return banks; in bank_characteristics()
849 weight_vector_type *banks = bank_characteristics(map); in optimize_reg_permutation() local
865 delta_conflicts(banks[bank_r], banks[bank_s], conflicts[r]) + in optimize_reg_permutation()
866 delta_conflicts(banks[bank_ in optimize_reg_permutation()
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/third_party/node/deps/brotli/c/enc/
H A Dhash_forgetful_chain_inc.h64 /* FN(Bank) banks[NUM_BANKS]; */
136 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in Store() local
143 banks[bank].slots[idx].delta = (uint16_t)delta; in Store()
144 banks[bank].slots[idx].next = head[key]; in Store()
202 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in FindLongestMatch() local
254 slot = banks[bank].slots[last].next; in FindLongestMatch()
255 delta = banks[bank].slots[last].delta; in FindLongestMatch()
/third_party/skia/third_party/externals/brotli/c/enc/
H A Dhash_forgetful_chain_inc.h64 /* FN(Bank) banks[NUM_BANKS]; */
136 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in Store() local
143 banks[bank].slots[idx].delta = (uint16_t)delta; in Store()
144 banks[bank].slots[idx].next = head[key]; in Store()
202 FN(Bank)* BROTLI_RESTRICT banks = FN(Banks)(self->extra); in FindLongestMatch() local
254 slot = banks[bank].slots[last].next; in FindLongestMatch()
255 delta = banks[bank].slots[last].delta; in FindLongestMatch()
/third_party/pulseaudio/speex/tmv/
H A Dfilterbank_tm.h43 register int i, j, k, banks, len, zero, s; in filterbank_compute_bank32() local
63 banks = bank->nb_banks << 2; in filterbank_compute_bank32()
72 for ( i=0 ; i<banks ; i+=4 ) in filterbank_compute_bank32()
209 register int i, banks, len; in filterbank_compute_bank32() local
213 banks = bank->nb_banks; in filterbank_compute_bank32()
222 memset(mel, 0, banks * sizeof(float)); in filterbank_compute_bank32()
/third_party/mesa3d/src/amd/addrlib/src/core/
H A Daddrlib1.cpp1290 const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes; in ComputeHtileInfo()
1925 baseAlign *= pTileInfo->banks; in ComputeCmaskBaseAlign()
2763 UINT_32 numPipes ///< [in] number of banks in ComputePipeFromAddr()
/third_party/mesa3d/src/amd/common/
H A Dac_surface.c918 surf->u.legacy.num_banks = csio->pTileInfo->banks; in gfx6_surface_settings()
1175 AddrTileInfoIn.banks = surf->u.legacy.num_banks; in gfx6_compute_surface()
/third_party/mesa3d/src/amd/addrlib/inc/
H A Daddrinterface.h149 UINT_32 numBanksLog2 : 3; ///< Number of banks log2
338 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK
453 UINT_32 banks; ///< Number of banks, numerical value member
1674 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1767 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!

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