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Searched refs:align_offset (Results 1 - 25 of 51) sorted by relevance

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/third_party/mesa3d/src/compiler/nir/
H A Dnir_lower_ubo_vec4.c94 unsigned align_offset = nir_intrinsic_align_offset(intr); in nir_lower_ubo_vec4_lower() local
103 align_offset &= 15; in nir_lower_ubo_vec4_lower()
104 assert(align_offset % chan_size_bytes == 0); in nir_lower_ubo_vec4_lower()
108 align_offset + chan_size_bytes * num_components <= 16); in nir_lower_ubo_vec4_lower()
120 int align_chan_offset = align_offset / chan_size_bytes; in nir_lower_ubo_vec4_lower()
137 align_offset + chan_size_bytes * intr->num_components <= 8) { in nir_lower_ubo_vec4_lower()
H A Dnir_lower_io.c1333 uint32_t align_mul, uint32_t align_offset, in build_explicit_io_load()
1343 align_mul, align_offset, in build_explicit_io_load()
1351 align_mul, align_offset, in build_explicit_io_load()
1357 align_mul, align_offset, in build_explicit_io_load()
1368 align_mul, align_offset, in build_explicit_io_load()
1375 align_mul, align_offset, in build_explicit_io_load()
1516 nir_intrinsic_set_align(load, align_mul, align_offset); in build_explicit_io_load()
1578 uint32_t align_mul, uint32_t align_offset, in build_explicit_io_store()
1587 align_mul, align_offset, in build_explicit_io_store()
1594 align_mul, align_offset, in build_explicit_io_store()
1330 build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin, nir_ssa_def *addr, nir_address_format addr_format, nir_variable_mode modes, uint32_t align_mul, uint32_t align_offset, unsigned num_components) build_explicit_io_load() argument
1575 build_explicit_io_store(nir_builder *b, nir_intrinsic_instr *intrin, nir_ssa_def *addr, nir_address_format addr_format, nir_variable_mode modes, uint32_t align_mul, uint32_t align_offset, nir_ssa_def *value, nir_component_mask_t write_mask) build_explicit_io_store() argument
1925 uint32_t align_mul, align_offset; nir_lower_explicit_io_instr() local
2016 nir_get_explicit_deref_align(nir_deref_instr *deref, bool default_to_type_align, uint32_t *align_mul, uint32_t *align_offset) nir_get_explicit_deref_align() argument
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H A Dnir_opt_load_store_vectorize.c193 uint32_t align_offset; member
572 entry->align_offset = entry->offset % entry->align_mul; in calc_alignment()
575 entry->align_offset = nir_intrinsic_align_offset(entry->intrin); in calc_alignment()
675 low->align_offset, in new_bitsize_acceptable()
816 first->align_offset = low->align_offset; in vectorize_loads()
902 second->align_offset = low->align_offset; in vectorize_stores()
1082 uint64_t max_low = round_down(UINT64_MAX, low->align_mul) + low->align_offset; in check_for_robustness()
1214 if (low->align_mul % low_size || low->align_offset in try_vectorize_shared2()
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H A Dnir_instr_set.c177 hash = HASH(hash, instr->cast.align_offset); in hash_deref()
634 deref1->cast.align_offset != deref2->cast.align_offset) in nir_instrs_equal()
H A Dnir.h1557 unsigned align_offset;
1929 unsigned align_mul, unsigned align_offset)
1932 assert(align_offset < align_mul);
1934 nir_intrinsic_set_align_offset(intrin, align_offset);
1948 const unsigned align_offset = nir_intrinsic_align_offset(intrin);
1949 assert(align_offset < align_mul);
1950 return align_offset ? 1 << (ffs(align_offset) - 1) : align_mul;
4789 uint32_t *align_offset);
5584 unsigned align_offset,
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H A Dnir_opt_large_constants.c89 .align_offset = 0); in build_constant_load()
/third_party/pcre2/pcre2/src/
H A Dpcre2_jit_neon_inc.h190 sljit_s32 align_offset = ((uint64_t)str_ptr & 0xf); in FF_FUN() local
240 if (align_offset < 8) in FF_FUN()
242 qw.dw[0] >>= align_offset * 8; in FF_FUN()
245 str_ptr += align_offset + __builtin_ctzll(qw.dw[0]) / 8; in FF_FUN()
256 qw.dw[1] >>= (align_offset - 8) * 8; in FF_FUN()
259 str_ptr += align_offset + __builtin_ctzll(qw.dw[1]) / 8; in FF_FUN()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_instr_export.cpp151 int align, int align_offset, int writemask, in ScratchIOInstr()
156 m_align_offset(align_offset), in ScratchIOInstr()
169 int align, int align_offset,int writemask, in ScratchIOInstr()
174 m_align_offset(align_offset), in ScratchIOInstr()
262 auto align_offset = int_from_string_with_prefix(align_offset_str, "ALO:"); variable
288 return new ScratchIOInstr(value, addr_reg->as_register(), align, align_offset, writemask, array_size);
291 return new ScratchIOInstr(value, offset, align, align_offset, writemask);
150 ScratchIOInstr(const RegisterVec4& value, PRegister addr, int align, int align_offset, int writemask, int array_size, bool is_read) ScratchIOInstr() argument
168 ScratchIOInstr(const RegisterVec4& value, int loc, int align, int align_offset,int writemask, bool is_read) ScratchIOInstr() argument
H A Dsfn_instr_export.h96 int align, int align_offset, int writemask, int array_size,
98 ScratchIOInstr(const RegisterVec4& value, int addr, int align, int align_offset,
H A Dsfn_shader.cpp933 int align_offset = nir_intrinsic_align_offset(intr); in emit_store_scratch() local
949 ws_ir = new ScratchIOInstr(value, offset, align, align_offset, writemask); in emit_store_scratch()
956 ws_ir = new ScratchIOInstr(value, addr_temp, align, align_offset, writemask, m_scratch_size); in emit_store_scratch()
980 int align_offset = nir_intrinsic_align_offset(intr); in emit_load_scratch() local
996 ir = new ScratchIOInstr(dest, offset, align, align_offset, 0xf, true); in emit_load_scratch()
1003 ir = new ScratchIOInstr(dest, addr_temp, align, align_offset, 0xf, in emit_load_scratch()
/third_party/mesa3d/src/gallium/drivers/etnaviv/tests/
H A Dlower_ubo_tests.cpp143 nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range = 8); in TEST_F()
158 nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range = 8); in TEST_F()
175 nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range = 8); in TEST_F()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_rt_common.c109 .align_offset = child_offset % 64); in intersect_ray_amd_software_box()
113 .align_mul = 64, .align_offset = coord_offsets[0] % 64), in intersect_ray_amd_software_box()
115 .align_mul = 64, .align_offset = coord_offsets[1] % 64), in intersect_ray_amd_software_box()
193 .align_offset = coord_offsets[0] % 64), in intersect_ray_amd_software_tri()
195 .align_offset = coord_offsets[1] % 64), in intersect_ray_amd_software_tri()
197 .align_offset = coord_offsets[2] % 64), in intersect_ray_amd_software_tri()
396 .align_mul = 64, .align_offset = offset + i * 16); in nir_build_wto_matrix_load()
H A Dradv_nir_lower_ray_queries.c371 .align_mul = 64, .align_offset = 0); in lower_rq_initialize()
439 .align_offset = 16), in lower_rq_load()
441 .align_offset = 32), in lower_rq_load()
443 .align_offset = 48)}; in lower_rq_load()
721 b, 4, 32, instance_node_addr, .align_mul = 64, .align_offset = 0); in lower_rq_proceed()
736 .align_mul = 64, .align_offset = 16), in lower_rq_proceed()
738 .align_mul = 64, .align_offset = 32), in lower_rq_proceed()
740 .align_mul = 64, .align_offset = 48)}; in lower_rq_proceed()
H A Dradv_pipeline_rt.c642 .align_mul = 64, .align_offset = 16), in lower_rt_instructions()
645 .align_mul = 64, .align_offset = 32), in lower_rt_instructions()
648 .align_mul = 64, .align_offset = 48)}; in lower_rt_instructions()
1486 .align_mul = 64, .align_offset = 16), in build_traversal_shader()
1488 .align_mul = 64, .align_offset = 32), in build_traversal_shader()
1490 .align_mul = 64, .align_offset = 48)}; in build_traversal_shader()
/third_party/mesa3d/src/amd/common/
H A Dac_nir_lower_tess_io_to_mem.c260 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_ls_output_store()
418 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_hs_per_vertex_input_load()
457 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_hs_output_store()
475 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_hs_output_load()
575 .align_mul = 16u, .align_offset = st->tcs_tess_lvl_out_loc % 16u); in hs_emit_write_tess_factors()
578 .align_mul = 16u, .align_offset = st->tcs_tess_lvl_in_loc % 16u) in hs_emit_write_tess_factors()
H A Dac_nir_lower_esgs_io_to_mem.c178 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_es_output_store()
279 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_gs_per_vertex_input_load()
/third_party/mesa3d/src/intel/vulkan/
H A Danv_nir_lower_ubo_loads.c98 .align_offset = nir_intrinsic_align_offset(load)); in lower_ubo_load_instr()
108 .align_offset = nir_intrinsic_align_offset(load)); in lower_ubo_load_instr()
H A Danv_nir_apply_pipeline_layout.c264 .align_offset = desc_offset % 8); in build_load_descriptor_mem()
275 .align_offset = desc_offset % 8, in build_load_descriptor_mem()
930 cast->cast.align_offset = 0; in lower_load_vulkan_descriptor()
936 cast->cast.align_offset = 0; in lower_load_vulkan_descriptor()
1099 .align_offset = 0, in lower_load_constant()
/third_party/mesa3d/src/gallium/drivers/virgl/
H A Dvirgl_resource.c346 unsigned align_offset; in virgl_staging_map() local
366 * |---| ==> align_offset in virgl_staging_map()
367 * |------------| ==> allocation of size + align_offset in virgl_staging_map()
369 align_offset = vres->b.target == PIPE_BUFFER ? in virgl_staging_map()
374 virgl_staging_alloc(&vctx->staging, size + align_offset, in virgl_staging_map()
381 * if we have an align_offset (see above for more information). */ in virgl_staging_map()
382 vtransfer->copy_src_offset += align_offset; in virgl_staging_map()
383 map_addr += align_offset; in virgl_staging_map()
399 vctx->queued_staging_res_size += size + align_offset; in virgl_staging_map()
/third_party/mesa3d/src/microsoft/vulkan/
H A Ddzn_nir.c144 .align_mul = 4, .align_offset = 0, .range_base = 0, .range = ~0); in dzn_nir_indirect_draw_shader()
234 .align_mul = 4, .align_offset = 0, .range_base = 0, .range = ~0); in dzn_nir_indirect_draw_shader()
333 .align_mul = 4, .align_offset = 0, .range_base = 0, .range = ~0); in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
497 .align_mul = 4, .align_offset = 0, .range_base = 0, .range = ~0); in dzn_nir_triangle_fan_rewrite_index_shader()
587 .align_mul = 16, .align_offset = 0, .range_base = 0, .range = ~0); in dzn_nir_blit_vs()
593 .align_mul = 64, .align_offset = 0, .range_base = 0, .range = ~0); in dzn_nir_blit_vs()
/third_party/mesa3d/src/broadcom/vulkan/
H A Dv3dv_image.c213 uint32_t align_offset = in v3d_setup_slices() local
215 if (align_offset) { in v3d_setup_slices()
216 image->size += align_offset; in v3d_setup_slices()
218 image->slices[i].offset += align_offset; in v3d_setup_slices()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_nir_lower_mem_access_bit_sizes.c170 const unsigned align_offset = nir_intrinsic_align_offset(intrin); in lower_mem_store_bit_size() local
210 (align_mul >= 4 && (align_offset + start) % 4 == 0) || in lower_mem_store_bit_size()
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_nir.c35 ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, in ir3_nir_should_vectorize_mem() argument
44 align_offset % byte_size == 0 && in ir3_nir_should_vectorize_mem()
57 align_offset &= 15; in ir3_nir_should_vectorize_mem()
63 unsigned worst_start_offset = 16 - align_mul + align_offset; in ir3_nir_should_vectorize_mem()
/third_party/skia/modules/skottie/src/text/
H A DTextAdapter.cpp688 const auto align_offset = in fragmentMatrix() local
701 const auto path_distance = rel_pos.x + align_offset; in fragmentMatrix()
754 const auto align_offset = -total_tracking * align_factor(fText->fHAlign); in adjustLineProps() local
765 fragment_offset = align_offset + tracking_acc + track_before; in adjustLineProps()
/third_party/mesa3d/src/microsoft/clc/
H A Dclc_compiler.c640 unsigned align_mul = 0, align_offset = 0; in split_unaligned_loads_stores() local
641 nir_get_explicit_deref_align(deref, true, &align_mul, &align_offset); in split_unaligned_loads_stores()
643 unsigned alignment = align_offset ? 1 << (ffs(align_offset) - 1) : align_mul; in split_unaligned_loads_stores()

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