| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | me_cmp_neon.S | 67 addv h16, v16.8h // add up v16
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| H A D | h264pred_neon.S | 393 addv h0, v0.8h
408 addv h0, v0.8h
427 addv h0, v0.8h
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| H A D | vc1dsp_neon.S | 1479 addv s22, v22.4s
1522 addv s22, v22.4s
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| /third_party/ffmpeg/libswscale/aarch64/ |
| H A D | hscale.S | 234 addv s0, v0.4S // add up products of src and filter values
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| /third_party/node/deps/v8/src/diagnostics/mips/ |
| H A D | disasm-mips.cc | 2240 Format(instr, "addv.'t 'wd, 'ws, 'wt"); in DecodeTypeMsa3R()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 655 __ addv(b27, v23.V16B()); in GenerateTestSequenceNEON()
656 __ addv(b12, v20.V8B()); in GenerateTestSequenceNEON()
657 __ addv(h27, v30.V4H()); in GenerateTestSequenceNEON()
658 __ addv(h19, v14.V8H()); in GenerateTestSequenceNEON()
659 __ addv(s14, v27.V4S()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 778 TEST_NEON(addv_0, addv(b0, v1.V8B()))
779 TEST_NEON(addv_1, addv(b0, v1.V16B()))
780 TEST_NEON(addv_2, addv(h0, v1.V4H()))
781 TEST_NEON(addv_3, addv(h0, v1.V8H()))
782 TEST_NEON(addv_4, addv(s0, v1.V4S()))
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| H A D | test-simulator-aarch64.cc | 4951 DEFINE_TEST_NEON_ACROSS(addv, Basic)
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1191 void addv(const VRegister& vd, const VRegister& vn);
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| H A D | macro-assembler-arm64.h | 256 V(addv, Addv) \
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| H A D | assembler-arm64.cc | 2046 V(addv, NEON_ADDV, true) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1775 LogicVRegister addv(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4635 addv(vf, rd, rn);
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| H A D | simulator-logic-arm64.cc | 1171 LogicVRegister Simulator::addv(VectorFormat vform, LogicVRegister dst, in addv() function in v8::internal::Simulator
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | assembler-mips.cc | 3161 V(addv, ADDV) \
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 3909 LogicVRegister addv(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3043 void addv(const VRegister& vd, const VRegister& vn);
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| H A D | assembler-aarch64.cc | 5370 V(addv, NEON_ADDV) \
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| H A D | logic-aarch64.cc | 1249 LogicVRegister Simulator::addv(VectorFormat vform, in addv() function in vixl::aarch64::Simulator
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| H A D | macro-assembler-aarch64.h | 3003 V(addv, Addv) \
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| H A D | simulator-aarch64.cc | 7920 addv(vf, rd, rn); in Simulator()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | assembler-mips64.cc | 3369 V(addv, ADDV) \
|