Searched refs:addpl (Results 1 - 6 of 6) sorted by relevance
| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | startcode_armv6.S | 172 addpl RESULT, RESULT, #2
191 addpl RESULT, RESULT, #2
208 addpl RESULT, RESULT, #2
221 addpl RESULT, RESULT, #2
232 addpl RESULT, RESULT, #2
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| /third_party/vixl/tools/ |
| H A D | make_instruction_doc_aarch64.pl | 39 my @sves = qw/addvl addpl rdvl cntb cnth cntw cntd ctermeq ctermne setffr/;
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 199 addpl(xd, xn, static_cast<int>(multiplier)); in Addpl()
210 VIXL_ASSERT(xn.IsZero()); // Other cases were handled with `addpl`. in Addpl()
211 // There is no simple `rdpl` instruction, and `addpl` cannot accept xzr, so in Addpl()
215 addpl(xd, xd, static_cast<int>(multiplier)); in Addpl()
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| H A D | assembler-aarch64.h | 3664 void addpl(const Register& xd, const Register& xn, int imm6);
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| H A D | assembler-sve-aarch64.cc | 6412 void Assembler::addpl(const Register& xd, const Register& xn, int imm6) { in addpl() function in vixl::aarch64::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-sve-aarch64.cc | 194 "addpl x10, x0, #24"); in TEST()
196 "addpl x10, x0, #12"); in TEST()
198 "addpl x10, x0, #6"); in TEST()
200 "addpl x10, x0, #3"); in TEST()
6034 COMPARE(addpl(x20, x6, 0), "addpl x20, x6, #0"); in TEST()
6035 COMPARE(addpl(x21, x7, 31), "addpl x21, x7, #31"); in TEST()
6036 COMPARE(addpl(x22, x8, -32), "addpl x2 in TEST()
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