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Searched refs:Vm (Results 1 - 4 of 4) sorted by relevance

/third_party/node/deps/v8/src/execution/arm/
H A Dsimulator-arm.cc3935 void Unop(Simulator* simulator, int Vd, int Vm, std::function<T(T)> unop) { in Unop() argument
3938 simulator->get_neon_register<T, SIZE>(Vm, src); in Unop()
3946 void Binop(Simulator* simulator, int Vd, int Vm, int Vn, in Binop() argument
3951 simulator->get_neon_register<T, SIZE>(Vm, src2); in Binop()
3967 void Widen(Simulator* simulator, int Vd, int Vm) { in Widen() argument
3971 simulator->get_neon_register<T, kDoubleSize>(Vm, src); in Widen()
3979 void Abs(Simulator* simulator, int Vd, int Vm) { in Abs() argument
3980 Unop<T>(simulator, Vd, Vm, [](T x) { return std::abs(x); }); in Abs()
3984 void Neg(Simulator* simulator, int Vd, int Vm) { in Neg() argument
3985 Unop<T>(simulator, Vd, Vm, []( in Neg()
3992 SaturatingNarrow(Simulator* simulator, int Vd, int Vm) SaturatingNarrow() argument
4004 AddSat(Simulator* simulator, int Vd, int Vm, int Vn) AddSat() argument
4009 SubSat(Simulator* simulator, int Vd, int Vm, int Vn) SubSat() argument
4014 Zip(Simulator* simulator, int Vd, int Vm) Zip() argument
4031 Unzip(Simulator* simulator, int Vd, int Vm) Unzip() argument
4048 Transpose(Simulator* simulator, int Vd, int Vm) Transpose() argument
4062 Test(Simulator* simulator, int Vd, int Vm, int Vn) Test() argument
4068 Add(Simulator* simulator, int Vd, int Vm, int Vn) Add() argument
4073 Sub(Simulator* simulator, int Vd, int Vm, int Vn) Sub() argument
4123 Mul(Simulator* simulator, int Vd, int Vm, int Vn) Mul() argument
4135 ShiftLeft(Simulator* simulator, int Vd, int Vm, int shift) ShiftLeft() argument
4140 LogicalShiftRight(Simulator* simulator, int Vd, int Vm, int shift) LogicalShiftRight() argument
4145 ArithmeticShiftRight(Simulator* simulator, int Vd, int Vm, int shift) ArithmeticShiftRight() argument
4152 ShiftRight(Simulator* simulator, int Vd, int Vm, int shift, bool is_unsigned) ShiftRight() argument
4163 ShiftRightAccumulate(Simulator* simulator, int Vd, int Vm, int shift) ShiftRightAccumulate() argument
4169 ArithmeticShiftRightAccumulate(Simulator* simulator, int Vd, int Vm, int shift) ArithmeticShiftRightAccumulate() argument
4178 ShiftLeftAndInsert(Simulator* simulator, int Vd, int Vm, int shift) ShiftLeftAndInsert() argument
4192 ShiftRightAndInsert(Simulator* simulator, int Vd, int Vm, int shift) ShiftRightAndInsert() argument
4206 ShiftByRegister(Simulator* simulator, int Vd, int Vm, int Vn) ShiftByRegister() argument
4240 CompareEqual(Simulator* simulator, int Vd, int Vm, int Vn) CompareEqual() argument
4245 CompareGreater(Simulator* simulator, int Vd, int Vm, int Vn, bool ge) CompareGreater() argument
4262 MinMax(Simulator* simulator, int Vd, int Vm, int Vn, bool min) MinMax() argument
4273 PairwiseMinMax(Simulator* simulator, int Vd, int Vm, int Vn, bool min) PairwiseMinMax() argument
4287 PairwiseAdd(Simulator* simulator, int Vd, int Vm, int Vn) PairwiseAdd() argument
4301 PairwiseAddLong(Simulator* simulator, int Vd, int Vm) PairwiseAddLong() argument
4315 PairwiseAddAccumulateLong(Simulator* simulator, int Vd, int Vm) PairwiseAddAccumulateLong() argument
4330 MultiplyLong(Simulator* simulator, int Vd, int Vn, int Vm) MultiplyLong() argument
4382 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4406 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4488 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4510 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4574 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4593 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4610 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4637 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4666 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4683 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4703 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4737 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4771 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4849 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4872 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4978 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
4990 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDTwoOrThreeRegisters() local
5049 int Vd, Vm, Vn; DecodeAdvancedSIMDDataProcessing() local
5560 int Vm = instr->VFPMRegValue(q ? kSimd128Precision : kDoublePrecision); DecodeAdvancedSIMDDataProcessing() local
5584 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDDataProcessing() local
5625 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDDataProcessing() local
5643 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDDataProcessing() local
5662 int Vm = instr->VFPMRegValue(kSimd128Precision); DecodeAdvancedSIMDDataProcessing() local
5683 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDDataProcessing() local
5704 int Vm = instr->VFPMRegValue(kDoublePrecision); DecodeAdvancedSIMDDataProcessing() local
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/third_party/jsframework/runtime/main/util/
H A Dprops.js1 import Vm from '../model';
16 * @param {Vm} vm - Vm object.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp5669 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTD() local
5670 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTD()
5713 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTD()
5728 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTQ() local
5729 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTQ()
5772 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTQ()
5787 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeNEONComplexLane64Instruction() local
5788 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeNEONComplexLane64Instruction()
5802 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeNEONComplexLane64Instruction()
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.cc2897 // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0) in vmov()
2913 // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm in vmov()
2927 // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm in vmov()
3001 // 32-bit register codes are Vm:M
3002 // 64-bit register codes are M:Vm
3003 // where Vm is four bits, and M is a single bit.
3018 int D, Vd, M, Vm; in EncodeVCVT() local
3019 SplitRegCode(src_type, src_code, &Vm, &M); in EncodeVCVT()
3026 // Vd(15-12) | 101(11-9) | sz(8) | op(7) | 1(6) | M(5) | 0(4) | Vm(3-0) in EncodeVCVT()
3043 Vd * B12 | 0x5 * B9 | sz * B8 | op * B7 | B6 | M * B5 | Vm); in EncodeVCVT()
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