| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1237 Udiv(dst.W(), lhs.W(), rhs.W()); in emit_i32_divu()
1265 Udiv(scratch, lhs_w, rhs_w); in emit_i32_remu()
1303 Udiv(dst.gp().X(), lhs.gp().X(), rhs.gp().X()); in emit_i64_divu()
1335 Udiv(scratch, lhs_x, rhs_x); in emit_i64_remu()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringARM32.cpp | 457 case InstArithmetic::Udiv: in genTargetHelperCallFor()
475 case InstArithmetic::Udiv: in genTargetHelperCallFor()
507 case InstArithmetic::Udiv: in genTargetHelperCallFor()
2728 case InstArithmetic::Udiv: in lowerInt64Arithmetic()
2941 case InstArithmetic::Udiv: {
3316 case InstArithmetic::Udiv:
5459 case InstArithmetic::Udiv:
5468 NewShiftKind = ArithInst->getOp() == InstArithmetic::Udiv
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| H A D | IceTargetLoweringX8632.cpp | 1767 case InstArithmetic::Udiv: in lowerArithmetic()
1872 case InstArithmetic::Udiv: in lowerArithmetic()
1995 case InstArithmetic::Udiv: in lowerArithmetic()
2124 case InstArithmetic::Udiv: { in lowerArithmetic()
6859 case InstArithmetic::Udiv: in genTargetHelperCallFor()
6891 case InstArithmetic::Udiv: in genTargetHelperCallFor()
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| H A D | IceInstARM32.h | 423 Udiv, enumerator
1017 using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
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| H A D | IceConverter.cpp | 283 return convertArithInstruction(Instr, Ice::InstArithmetic::Udiv); in convertInstruction()
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| H A D | WasmTranslator.cpp | 442 Control()->appendInst(InstArithmetic::create(Func, InstArithmetic::Udiv, in Binop()
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| H A D | IceTargetLoweringMIPS32.cpp | 372 case InstArithmetic::Udiv: in genTargetHelperCallFor()
2693 case InstArithmetic::Udiv: in lowerInt64Arithmetic()
2881 case InstArithmetic::Udiv: { in lowerArithmetic()
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| H A D | IceTargetLoweringX8664.cpp | 1795 case InstArithmetic::Udiv: in lowerArithmetic()
1924 case InstArithmetic::Udiv: { in lowerArithmetic()
6179 case InstArithmetic::Udiv: in genTargetHelperCallFor()
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| H A D | IceInstARM32.cpp | 3420 template class InstARM32ThreeAddrGPR<InstARM32::Udiv>;
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| H A D | PNaClTranslator.cpp | 1784 Op = Ice::InstArithmetic::Udiv; in convertBinopOpcode()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1327 __ Udiv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction()
1330 __ Udiv(i.OutputRegister32(), i.InputRegister32(0), i.InputRegister32(1)); in AssembleArchInstruction()
1350 __ Udiv(temp, i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction()
1357 __ Udiv(temp, i.InputRegister32(0), i.InputRegister32(1)); in AssembleArchInstruction()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 1427 __ Udiv(w0, w16, w16); in TEST()
1428 __ Udiv(w1, w17, w16); in TEST()
1433 __ Udiv(x5, x16, x16); in TEST()
1434 __ Udiv(x6, x17, x18); in TEST()
1439 __ Udiv(w10, w19, w21); in TEST()
1441 __ Udiv(x12, x19, x21); in TEST()
1443 __ Udiv(x14, x20, x21); in TEST()
1446 __ Udiv(w22, w19, w17); in TEST()
1448 __ Udiv(x24, x20, x18); in TEST()
1451 __ Udiv(x2 in TEST()
[all...] |
| H A D | test-disasm-sve-aarch64.cc | 2469 COMPARE_MACRO(Udiv(z27.VnS(), p5.Merging(), z16.VnS(), z27.VnS()), in TEST()
2471 COMPARE_MACRO(Udiv(z13.VnD(), p4.Merging(), z22.VnD(), z11.VnD()), in TEST()
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| H A D | test-assembler-sve-aarch64.cc | 5026 ArithPredicatedFn fn = &MacroAssembler::Udiv;
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 997 void TurboAssembler::Udiv(const Register& rd, const Register& rn, in Udiv() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64.h | 1044 inline void Udiv(const Register& rd, const Register& rn, const Register& rm);
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 679 V(Udiv, udiv) \
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| H A D | macro-assembler-aarch64.h | 2729 void Udiv(const Register& rd, const Register& rn, const Register& rm) { in Udiv() function in vixl::aarch64::MacroAssembler
6271 void Udiv(const ZRegister& zd,
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| /third_party/vixl/test/aarch32/ |
| H A D | test-simulator-cond-rd-rn-rm-a32.cc | 143 M(Udiv) \
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| H A D | test-simulator-cond-rd-rn-rm-t32.cc | 142 M(Udiv) \
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 5821 void Udiv(Condition cond, Register rd, Register rn, Register rm) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
5835 void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); } in MacroAssembler() function in vixl::aarch32::MacroAssembler
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| /third_party/skia/third_party/externals/swiftshader/src/Reactor/ |
| H A D | SubzeroReactor.cpp | 1250 return createArithmetic(Ice::InstArithmetic::Udiv, lhs, rhs);
|