Searched refs:TGSI_WRITEMASK_ZW (Results 1 - 16 of 16) sorted by relevance
| /third_party/mesa3d/src/gallium/auxiliary/vl/ |
| H A D | vl_deint_filter.c | 107 ureg_MOV(shader, ureg_writemask(t_tex, TGSI_WRITEMASK_ZW), in create_copy_frag_shader()
110 ureg_MOV(shader, ureg_writemask(t_tex, TGSI_WRITEMASK_ZW), in create_copy_frag_shader()
162 ureg_MOV(shader, ureg_writemask(t_tex, TGSI_WRITEMASK_ZW), in create_deint_frag_shader()
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| H A D | vl_matrix_filter.c | 114 ureg_MOV(shader, ureg_writemask(tmp, TGSI_WRITEMASK_ZW), in create_frag_shader()
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| H A D | vl_mc.c | 76 ureg_MOV(shader, ureg_writemask(o_vpos, TGSI_WRITEMASK_ZW), ureg_imm1f(shader, 1.0f)); in calc_position()
149 ureg_MUL(shader, ureg_writemask(o_vmv[i], TGSI_WRITEMASK_ZW), mv_scale, vmv[i]); in create_ref_vert_shader()
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| H A D | vl_median_filter.c | 130 ureg_MOV(shader, ureg_writemask(t_array[i], TGSI_WRITEMASK_ZW), in create_frag_shader()
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| H A D | vl_idct.c | 179 ureg_MOV(shader, ureg_writemask(o_vpos, TGSI_WRITEMASK_ZW), ureg_imm1f(shader, 1.0f)); in create_mismatch_vert_shader()
305 ureg_MOV(shader, ureg_writemask(o_vpos, TGSI_WRITEMASK_ZW), ureg_imm1f(shader, 1.0f)); in create_stage1_vert_shader()
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| H A D | vl_bicubic_filter.c | 220 ureg_MOV(shader, ureg_writemask(t_array[i], TGSI_WRITEMASK_ZW), in create_frag_shader()
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| H A D | vl_zscan.c | 165 ureg_MOV(shader, ureg_writemask(o_vpos, TGSI_WRITEMASK_ZW), ureg_imm1f(shader, 1.0f)); in create_vert_shader()
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| /third_party/mesa3d/src/gallium/include/pipe/ |
| H A D | p_shader_tokens.h | 95 #define TGSI_WRITEMASK_ZW 0x0C macro
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_util.c | 219 (write_mask & TGSI_WRITEMASK_ZW ? TGSI_WRITEMASK_Z : 0); in tgsi_util_get_src_usage_mask()
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| H A D | tgsi_exec.c | 3463 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) { in exec_double_unary()
3497 if (wmask & TGSI_WRITEMASK_ZW) { in exec_double_binary()
3527 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) { in exec_double_trinary()
3553 if (wmask & TGSI_WRITEMASK_ZW) { in exec_dldexp()
3573 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) in exec_dfracexp()
3599 if (wmask & TGSI_WRITEMASK_ZW) { in exec_arg0_64_arg1_32()
4251 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) in exec_t_2_64()
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| /third_party/mesa3d/src/gallium/auxiliary/nir/ |
| H A D | nir_to_tgsi.c | 642 tgsi_usage_mask |= TGSI_WRITEMASK_ZW; in ntt_tgsi_usage_mask()
1463 assert(!(dst.WriteMask & TGSI_WRITEMASK_ZW)); in ntt_emit_alu()
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| /third_party/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| H A D | nv50_surface.c | 1015 mask &= ~TGSI_WRITEMASK_ZW; in nv50_blitter_make_fp()
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| /third_party/mesa3d/src/gallium/drivers/svga/ |
| H A D | svga_tgsi_insn.c | 3265 writemask(depth, TGSI_WRITEMASK_ZW), in emit_vs_postamble()
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| H A D | svga_tgsi_vgpu10.c | 9330 writemask == TGSI_WRITEMASK_ZW); in check_double_dst_writemask()
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| /third_party/mesa3d/src/gallium/frontends/nine/ |
| H A D | nine_ff.c | 694 ureg_MOV(ureg, ureg_writemask(input_coord, TGSI_WRITEMASK_ZW), ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f)); in nine_ff_build_vs()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | r600_shader.c | 5115 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW); in cayman_emit_double_instr()
5233 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW); in cayman_mul_double_instr()
5286 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW); in cayman_ddiv_instr()
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