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Searched refs:Spill (Results 1 - 25 of 27) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp332 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
335 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
336 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
340 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
348 Spill.FullyAllocated = true; in allocateVGPRSpillToAGPR()
376 Spill.FullyAllocated = false; in allocateVGPRSpillToAGPR()
382 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
385 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
H A DSIFrameLowering.cpp756 ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill in emitPrologue() local
758 assert(Spill.size() == 1); in emitPrologue()
763 Spill[0].VGPR) in emitPrologue()
765 .addImm(Spill[0].Lane) in emitPrologue()
766 .addReg(Spill[0].VGPR, RegState::Undef); in emitPrologue()
860 ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill in emitEpilogue() local
862 assert(Spill.size() == 1); in emitEpilogue()
865 .addReg(Spill[0].VGPR) in emitEpilogue()
866 .addImm(Spill[0].Lane); in emitEpilogue()
1027 auto Spill in determineCalleeSaves()
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H A DSIMachineFunctionInfo.h751 void setHasSpilledSGPRs(bool Spill = true) { in setHasSpilledSGPRs()
752 HasSpilledSGPRs = Spill; in setHasSpilledSGPRs()
759 void setHasSpilledVGPRs(bool Spill = true) { in setHasSpilledVGPRs()
760 HasSpilledVGPRs = Spill; in setHasSpilledVGPRs()
H A DSIRegisterInfo.cpp791 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
798 VGPRDefined = !SGPRSpillVGPRDefinedSet.insert(Spill.VGPR).second; in spillSGPR()
804 Spill.VGPR) in spillSGPR()
806 .addImm(Spill.Lane) in spillSGPR()
807 .addReg(Spill.VGPR, VGPRDefined ? 0 : RegState::Undef); in spillSGPR()
817 // Spill SGPR to a frame index. in spillSGPR()
892 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
896 .addReg(Spill.VGPR) in restoreSGPR()
897 .addImm(Spill.Lane); in restoreSGPR()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DRegAllocBasic.cpp201 // Spill or split all live virtual registers currently unified under PhysReg
225 // Spill each interfering vreg allocated to PhysReg or an alias. in spillInterferences()
227 LiveInterval &Spill = *Intfs[i]; in spillInterferences() local
230 if (!VRM->hasPhys(Spill.reg)) in spillInterferences()
235 Matrix->unassign(Spill); in spillInterferences()
237 // Spill the extracted interval. in spillInterferences()
238 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in spillInterferences()
H A DInlineSpiller.cpp151 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
153 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
800 // Spill subregs if the target allows it. in foldMemoryOperand()
1059 /// spillAll - Spill all registers remaining after rematerialization.
1078 // Spill around uses of all RegsToSpill. in spillAll()
1138 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, in addToMergeableSpills() argument
1149 SlotIndex Idx = LIS.getInstructionIndex(Spill); in addToMergeableSpills()
1152 MergeableSpills[MIdx].insert(&Spill); in addToMergeableSpills()
1157 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill, in rmFromMergeableSpills() argument
1162 SlotIndex Idx = LIS.getInstructionIndex(Spill); in rmFromMergeableSpills()
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/third_party/node/deps/v8/src/maglev/
H A Dmaglev-regalloc.cc394 node->Spill(location); in AllocateNodeResult()
470 Spill(node); in DropRegisterValue()
581 void StraightForwardRegisterAllocator::Spill(ValueNode* node) { in Spill() function in v8::internal::maglev::StraightForwardRegisterAllocator
638 Spill(node); in SpillRegisters()
646 Spill(node); in SpillAndClearRegisters()
656 node->Spill(compiler::AllocatedOperand(compiler::AllocatedOperand::STACK_SLOT, in AllocateSpillSlot()
H A Dmaglev-regalloc.h79 void Spill(ValueNode* node);
H A Dmaglev-ir.h713 void Spill(compiler::AllocatedOperand operand) { in Spill() function in v8::internal::maglev::ValueNode
/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-assembler.cc115 asm_->Spill(dst.offset(), src.reg(), src.kind()); in TransferStackSlot()
118 asm_->Spill(dst.offset(), src.constant()); in TransferStackSlot()
321 asm_->Spill(last_spill_offset, spill_reg, move->kind); in ExecuteMoves()
731 Spill(slot.offset(), slot.constant()); in MaterializeMergedConstants()
868 void LiftoffAssembler::Spill(VarState* slot) { in Spill() function in v8::internal::wasm::LiftoffAssembler
873 Spill(slot->offset(), slot->reg(), slot->kind()); in Spill()
877 Spill(slot->offset(), slot->constant()); in Spill()
885 Spill(&cache_state_.stack_state[i]); in SpillLocals()
893 Spill(slot.offset(), slot.reg(), slot.kind()); in SpillAllRegisters()
1014 // Spill al in PrepareCall()
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H A Dliftoff-assembler.h597 void Spill(VarState* slot);
801 inline void Spill(int offset, LiftoffRegister, ValueKind);
802 inline void Spill(int offset, WasmValue);
1547 // Spill one or two fp registers to get a pair of adjacent fp registers.
H A Dliftoff-compiler.cc761 __ Spill(liftoff::kTierupBudgetOffset, budget_reg, ValueKind::kI32); in TierupCheck()
845 __ Spill(liftoff::kFeedbackVectorOffset, tmp, kPointerKind); in StartFunctionBody()
856 __ Spill(liftoff::kTierupBudgetOffset, tmp, ValueKind::kI32); in StartFunctionBody()
891 __ Spill(__ cache_state()->stack_state[local_index].offset(), in StartFunctionBody()
958 __ Spill(entry.offset, entry.reg, entry.kind); in GenerateOutOfLineCode()
987 __ Spill(liftoff::kTierupBudgetOffset, in GenerateOutOfLineCode()
6198 // Spill everything up front to work around that.
/third_party/node/deps/v8/src/compiler/backend/
H A Dmid-tier-register-allocator.cc310 // Spill an operand that is assigned to this virtual register.
765 // Spill the contents of |reg| for an instruction in |current_block| using
767 void Spill(RegisterIndex reg, AllocatedOperand allocated,
848 void Spill(AllocatedOperand allocated_op,
1058 void RegisterState::Register::Spill(AllocatedOperand allocated_op, in Spill() function in v8::internal::compiler::RegisterState::Register
1110 // Spill all the pending operands associated with this register. in SpillPendingUses()
1176 void RegisterState::Spill(RegisterIndex reg, AllocatedOperand allocated, in Spill() function in v8::internal::compiler::RegisterState
1180 reg_data(reg).Spill(allocated, current_block, data); in Spill()
1433 // Spill a register in a previously processed successor block when merging
1852 // Spill th in MergeStateFrom()
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H A Dregister-allocator.cc374 void LiveRange::Spill() { in Spill() function in v8::internal::compiler::LiveRange
1178 // Spill ranges are created for top level. This is so that, when merging in SpillRange()
1804 // Spill at every use position for simplicity, this case is very rare. in MeetConstraintsBefore()
2839 Spill(range, SpillMode::kSpillAtDefinition); in SplitAndSpillRangesDefinedByMemoryOperand()
2852 Spill(range, SpillMode::kSpillAtDefinition); in SplitAndSpillRangesDefinedByMemoryOperand()
2978 void RegisterAllocator::Spill(LiveRange* range, SpillMode spill_mode) { in Spill() function in v8::internal::compiler::RegisterAllocator
3000 range->Spill(); in Spill()
3030 // Spill begin_range after begin_pos, then spill every live range of this in MaybeSpillPreviousRanges()
3043 range->Spill(); in MaybeSpillPreviousRanges()
3116 Spill(spli in SpillNotLiveRanges()
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H A Dregister-allocator.h578 void Spill();
856 // Spill range management.
1098 // Spill slots can be 4, 8, or 16 bytes wide.
1349 void Spill(LiveRange* range, SpillMode spill_mode);
1497 // Spill the given life range after position pos.
1500 // Spill the given life range after position [start] and up to position [end].
1504 // Spill the given life range after position [start] and up to position [end].
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Coroutines/
H A DCoroFrame.cpp289 class Spill { class
295 Spill(Value *Def, llvm::User *U) : Def(Def), User(cast<Instruction>(U)) {} in Spill() function in __anon24983::Spill
319 using SpillInfo = SmallVector<Spill, 8>;
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringX8632.cpp2908 Variable *Spill = Func->makeVariable(IceType_f64); in lowerCast() local
2909 Spill->setLinkedTo(Src0Var); in lowerCast()
2910 Spill->setMustNotHaveReg(); in lowerCast()
2911 _movq(Spill, Src0RM); in lowerCast()
2912 SpillLo = VariableSplit::create(Func, Spill, VariableSplit::Low); in lowerCast()
2913 SpillHi = VariableSplit::create(Func, Spill, VariableSplit::High); in lowerCast()
2945 Variable *Spill = Func->makeVariable(IceType_f64); in lowerCast() local
2946 Spill->setLinkedTo(Dest); in lowerCast()
2947 Spill->setMustNotHaveReg(); in lowerCast()
2950 auto *SpillLo = VariableSplit::create(Func, Spill, VariableSpli in lowerCast()
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/third_party/node/deps/v8/src/wasm/baseline/mips/
H A Dliftoff-assembler-mips.h794 Spill(dst_offset, reg, kind); in MoveStackValue()
808 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
833 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler
/third_party/node/deps/v8/src/wasm/baseline/loong64/
H A Dliftoff-assembler-loong64.h851 Spill(dst_offset, reg, kind); in MoveStackValue()
870 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
897 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler
/third_party/node/deps/v8/src/wasm/baseline/mips64/
H A Dliftoff-assembler-mips64.h955 Spill(dst_offset, reg, kind); in MoveStackValue()
974 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
1001 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler
/third_party/node/deps/v8/src/wasm/baseline/ppc/
H A Dliftoff-assembler-ppc.h954 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
983 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler
/third_party/node/deps/v8/src/wasm/baseline/arm64/
H A Dliftoff-assembler-arm64.h932 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
938 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler
/third_party/node/deps/v8/src/wasm/baseline/s390/
H A Dliftoff-assembler-s390.h1407 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
1438 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h1389 Spill(dst_offset, reg, kind); in MoveStackValue()
1411 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
1422 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler
/third_party/node/deps/v8/src/wasm/baseline/riscv64/
H A Dliftoff-assembler-riscv64.h969 Spill(dst_offset, reg, kind); in MoveStackValue()
988 void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) { in Spill() function in v8::internal::wasm::LiftoffAssembler
1021 void LiftoffAssembler::Spill(int offset, WasmValue value) { in Spill() function in v8::internal::wasm::LiftoffAssembler

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