| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 2494 abs(vform, result, zn).SignedSaturate(vform); in Simulator()
2497 neg(vform, result, zn).SignedSaturate(vform); in Simulator()
3422 add(vform, result, zdn, zm).SignedSaturate(vform); in Simulator()
3425 sub(vform, result, zdn, zm).SignedSaturate(vform); in Simulator()
3428 sub(vform, result, zm, zdn).SignedSaturate(vform); in Simulator()
6990 abs(vf, rd, rn).SignedSaturate(vf); in Simulator()
6993 neg(vf, rd, rn).SignedSaturate(vf); in Simulator()
7547 add(vf, rd, rn, rm).SignedSaturate(vf); in Simulator()
7553 sub(vf, rd, rn, rm).SignedSaturate(vf); in Simulator()
7565 sshl(vf, rd, rn, rm).SignedSaturate(v in Simulator()
[all...] |
| H A D | logic-aarch64.cc | 1689 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform);
2006 neg(vform, temp, src2).SignedSaturate(vform);
2017 neg(vform, temp, src2).SignedSaturate(vform);
2277 return extractnarrow(vform, dst, true, src, true).SignedSaturate(vform);
2736 sub(vform, src1_r, src1_r, src2_i).SignedSaturate(vform);
2737 add(vform, src1_i, src1_i, src2_r).SignedSaturate(vform);
2745 add(vform, src1_r, src1_r, src2_i).SignedSaturate(vform);
2746 sub(vform, src1_i, src1_i, src2_r).SignedSaturate(vform);
3893 return add(vform, dst, dst, product).SignedSaturate(vform);
3912 return sub(vform, dst, dst, product).SignedSaturate(vfor
[all...] |
| H A D | simulator-aarch64.h | 911 LogicVRegister& SignedSaturate(VectorFormat vform) { in SignedSaturate() function in vixl::aarch64::LogicVRegister
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 3960 abs(vf, rd, rn).SignedSaturate(vf);
3963 neg(vf, rd, rn).SignedSaturate(vf);
4377 add(vf, rd, rn, rm).SignedSaturate(vf);
4383 sub(vf, rd, rn, rm).SignedSaturate(vf);
4395 sshl(vf, rd, rn, rm).SignedSaturate(vf);
4407 sshl(vf, rd, rn, rm).Round(vf).SignedSaturate(vf);
5367 abs(vf, rd, rn).SignedSaturate(vf);
5373 neg(vf, rd, rn).SignedSaturate(vf);
5580 add(vf, rd, rn, rm).SignedSaturate(vf);
5586 sub(vf, rd, rn, rm).SignedSaturate(v
[all...] |
| H A D | simulator-logic-arm64.cc | 1414 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform); in sqshl()
1816 return ExtractNarrow(vform, dst, true, src, true).SignedSaturate(vform); in sqxtn()
2678 return add(vform, dst, dst, product).SignedSaturate(vform); in sqdmlal()
2686 return add(vform, dst, dst, product).SignedSaturate(vform); in sqdmlal2()
2694 return sub(vform, dst, dst, product).SignedSaturate(vform); in sqdmlsl()
2702 return sub(vform, dst, dst, product).SignedSaturate(vform); in sqdmlsl2()
2710 return add(vform, dst, product, product).SignedSaturate(vform); in sqdmull()
2718 return add(vform, dst, product, product).SignedSaturate(vform); in sqdmull2()
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| H A D | simulator-arm64.h | 562 LogicVRegister& SignedSaturate(VectorFormat vform) { in SignedSaturate() function in v8::internal::LogicVRegister
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