| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-neon-aarch64.cc | 3912 COMPARE_MACRO(Scvtf(v5.V2S(), v3.V2S()), in TEST()
3915 COMPARE_MACRO(Scvtf(v6.V4S(), v4.V4S()), in TEST()
3918 COMPARE_MACRO(Scvtf(v7.V2D(), v5.V2D()), in TEST()
3921 COMPARE_MACRO(Scvtf(s8, s6), "scvtf s8, s6"); in TEST()
3922 COMPARE_MACRO(Scvtf(d8, d6), "scvtf d8, d6"); in TEST()
3991 COMPARE_2REGMISC_FP16(Scvtf, "scvtf"); in TEST()
4419 COMPARE_MACRO(Scvtf(v5.V4H(), v3.V4H(), 11), "scvtf v5.4h, v3.4h, #11"); in TEST()
4420 COMPARE_MACRO(Scvtf(v6.V8H(), v4.V8H(), 12), "scvtf v6.8h, v4.8h, #12"); in TEST()
4421 COMPARE_MACRO(Scvtf(v5.V2S(), v3.V2S(), 11), "scvtf v5.2s, v3.2s, #11"); in TEST()
4422 COMPARE_MACRO(Scvtf(v in TEST()
[all...] |
| H A D | test-assembler-fp-aarch64.cc | 4636 __ Scvtf(d0, x10);
4638 __ Scvtf(d2, w11);
4647 __ Scvtf(d0, x10, fbits);
4649 __ Scvtf(d2, w11, fbits);
4660 __ Scvtf(d0, x10, fbits);
4791 __ Scvtf(s0, x10);
4793 __ Scvtf(s2, w11);
4802 __ Scvtf(s0, x10, fbits);
4804 __ Scvtf(s2, w11, fbits);
4815 __ Scvtf(s
[all...] |
| H A D | test-assembler-sve-aarch64.cc | 14515 __ Scvtf(z7.VnH(), p0.Merging(), z7.VnH()); // Ai + B
14559 __ Scvtf(z11.VnS(), p0.Merging(), z11.VnS());
14580 __ Scvtf(z15.VnD(), p0.Merging(), z15.VnD());
14624 __ Scvtf(z1.VnH(), p0.Merging(), z1.VnH());
14659 __ Scvtf(z1.VnS(), p0.Merging(), z1.VnS());
14706 __ Scvtf(z1.VnH(), p0.Merging(), z1.VnH());
14749 __ Scvtf(z1.VnS(), p0.Merging(), z1.VnS());
14770 __ Scvtf(z1.VnD(), p0.Merging(), z1.VnD());
14805 masm->Scvtf(ztmp, ptrue, ztmp);
15214 __ Scvtf(z
[all...] |
| H A D | test-simulator-aarch64.cc | 2978 // TODO: Scvtf-fixed-point
2979 // TODO: Scvtf-integer
5102 __ Scvtf(temp, input_2); in GenerateSum()
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1401 Scvtf(fp_cmp, dst.gp().W()); // i32 -> f64. in emit_type_conversion()
1491 Scvtf(dst.fp().S(), src.gp().W()); in emit_type_conversion()
1497 Scvtf(dst.fp().S(), src.gp().X()); in emit_type_conversion()
1509 Scvtf(dst.fp().D(), src.gp().W()); in emit_type_conversion()
1515 Scvtf(dst.fp().D(), src.gp().X()); in emit_type_conversion()
1905 Scvtf(dst.fp().V2D(), dst.fp().V2D()); in emit_f64x2_convert_low_i32x4_s()
2926 Scvtf(dst.fp().V4S(), src.fp().V4S()); in emit_i8x16_bitmask()
|
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1795 __ Scvtf(i.OutputFloat32Register(), i.InputRegister32(0)); in AssembleArchInstruction()
1798 __ Scvtf(i.OutputDoubleRegister(), i.InputRegister32(0)); in AssembleArchInstruction()
1801 __ Scvtf(i.OutputDoubleRegister().S(), i.InputRegister64(0)); in AssembleArchInstruction()
1804 __ Scvtf(i.OutputDoubleRegister(), i.InputRegister64(0)); in AssembleArchInstruction()
2210 __ Scvtf(dst, dst); in AssembleArchInstruction()
2299 SIMD_UNOP_CASE(kArm64F32x4SConvertI32x4, Scvtf, 4S); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 1131 inline void Scvtf(const VRegister& fd, const Register& rn,
1133 void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Scvtf() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64-inl.h | 911 void TurboAssembler::Scvtf(const VRegister& fd, const Register& rn, in Scvtf() function in v8::internal::TurboAssembler
|
| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 2431 void Scvtf(const VRegister& vd, const Register& rn, int fbits = 0) { in Scvtf() function in vixl::aarch64::MacroAssembler
3496 void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Scvtf() function in vixl::aarch64::MacroAssembler
5800 void Scvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Scvtf() function in vixl::aarch64::MacroAssembler
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