| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 463 SXTH, enumerator
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| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 83 COMPARE_MACRO(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); in TEST()
339 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); in TEST()
343 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); in TEST()
365 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); in TEST()
2467 COMPARE_MACRO(Csel(x3, x4, Operand(x5, SXTH), eq), in TEST()
2472 Operand(x5, SXTH), in TEST()
2487 COMPARE_MACRO(Csel(x9, Operand(x10, SXTH), x11, eq), in TEST()
2491 Operand(x10, SXTH), in TEST()
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| H A D | test-assembler-aarch64.cc | 191 __ Mvn(x13, Operand(x2, SXTH, 3)); in TEST()
365 __ Mov(x26, Operand(x13, SXTH, 3)); in TEST()
419 __ Mov(w22, Operand(w11, SXTH, 1)); in TEST()
426 __ Mov(x28, Operand(x12, SXTH, 1)); in TEST()
502 __ Orr(x11, x0, Operand(x1, SXTH, 1)); in TEST()
596 __ Orn(x11, x0, Operand(x1, SXTH, 1)); in TEST()
663 __ And(x11, x0, Operand(x1, SXTH, 1)); in TEST()
809 __ Bic(x11, x0, Operand(x1, SXTH, 1)); in TEST()
941 __ Eor(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1008 __ Eon(x11, x0, Operand(x1, SXTH, in TEST()
[all...] |
| H A D | test-api-aarch64.cc | 1009 VIXL_CHECK(!Operand(w14, SXTH).IsPlainRegister()); in TEST()
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| H A D | test-cpu-features-aarch64.cc | 482 TEST_NONE(subs_0, subs(w0, w1, Operand(w2, SXTH, 0)))
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 302 STORE_OPCODE(SEXT16, SXTH); in OpcodeCache()
|
| H A D | ARMFastISel.cpp | 2662 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2902 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
|
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 132 return Operand(InputRegister32(index), SXTH); in InputOperand2_32()
162 return Operand(InputRegister64(index), SXTH); in InputOperand2_64()
|
| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeARM_32.c | 145 #define SXTH 0xe6bf0070 macro
1473 return push_inst(compiler, (op == SLJIT_MOV_U16 ? UXTH : SXTH) | RD(dst) | RM(src2)); in emit_single_op()
|
| H A D | sljitNativeARM_T2_32.c | 185 #define SXTH 0xb200 macro
830 return push_inst16(compiler, SXTH | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1252 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
1265 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend64()
2755 .Case("sxth", AArch64_AM::SXTH) in tryParseOptionalShiftExtend()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 376 SXTH = 5, enumerator
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| H A D | assembler-arm64.cc | 3905 case SXTH: in EmitExtendShift()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 499 return AArch64_AM::SXTH; in getExtendTypeForNode()
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| H A D | AArch64InstructionSelector.cpp | 4726 return AArch64_AM::SXTH;
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| H A D | AArch64FastISel.cpp | 1177 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
|
| /third_party/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 364 SXTH = 5, enumerator
|
| H A D | assembler-aarch64.cc | 6235 case SXTH:
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| H A D | simulator-aarch64.cc | 1085 case SXTH: in Simulator()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 1144 case SXTH:
|