Searched refs:SI_SGPR_VS_STATE_BITS (Results 1 - 5 of 5) sorted by relevance
/third_party/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_state_draw.cpp | 794 /* Set SI_SGPR_VS_STATE_BITS. */ 1238 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state); 1244 radeon_set_sh_reg(gs_base + SI_SGPR_VS_STATE_BITS * 4, gs_state); 1248 radeon_set_sh_reg(gs_copy_base + SI_SGPR_VS_STATE_BITS * 4, gs_state); 1250 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state); 1251 radeon_set_sh_reg(tes_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state); 1253 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state);
|
H A D | si_shader.h | 179 SI_SGPR_VS_STATE_BITS = SI_NUM_RESOURCE_SGPRS, enumerator 867 /* SI_SGPR_VS_STATE_BITS */
|
H A D | si_shader_llvm_tess.c | 555 ret = si_insert_input_ret(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); in si_set_ls_return_value_for_tcs()
|
H A D | si_shader_llvm_gs.c | 69 ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); in si_set_es_return_value_for_gs()
|
H A D | gfx10_shader_ngg.c | 1434 ret = si_insert_input_ptr(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS); in gfx10_ngg_culling_build_end()
|
Completed in 11 milliseconds