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Searched refs:SHL (Results 1 - 25 of 104) sorted by relevance

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/third_party/node/deps/openssl/openssl/crypto/bn/asm/
H A Dc64xplus-gf2m.pl72 || SHL $Ahix0,16,$OUTlo
78 || SHL $Alox1,8,$Alox1
79 || SHL $Ahix3,8,$Ahix3
83 || SHL $Ahix1,24,$Alox1
100 || SHL $Ahix0,16,$OUTlo
104 || SHL $Alox1,8,$Alox1
105 || SHL $Ahix3,8,$Ahix3
108 || SHL $Ahix1,24,$Alox1
/third_party/openssl/crypto/bn/asm/
H A Dc64xplus-gf2m.pl72 || SHL $Ahix0,16,$OUTlo
78 || SHL $Alox1,8,$Alox1
79 || SHL $Ahix3,8,$Ahix3
83 || SHL $Ahix1,24,$Alox1
100 || SHL $Ahix0,16,$OUTlo
104 || SHL $Alox1,8,$Alox1
105 || SHL $Ahix3,8,$Ahix3
108 || SHL $Ahix1,24,$Alox1
H A Dbn-c64xplus.asm195 [!A2] SHL A6,A0,A6 ; normalize dv
199 ||[!A2] SHL A4,1,A5:A4 ; lo<<1
208 || SHL A4,1,A5:A4 ; lo<<1
/third_party/node/deps/openssl/openssl/crypto/sha/asm/
H A Dsha512-c64xplus.pl25 # it's effectively dominated by SHRU||SHL pairs and you can't schedule
166 || SHL $Ehi,32-14,$S1lo
172 || SHL $Elo,32-14,$t0hi
180 || SHL $Ehi,32-18,$t0lo
188 || SHL $Elo,32-18,$t0hi
196 || SHL $Ehi,64-41,$t0hi
204 || SHL $Elo,64-41,$t0lo
212 || SHL $Ahi,32-28,$S0lo
220 || SHL $Alo,32-28,$t0hi
228 || SHL
[all...]
/third_party/openssl/crypto/sha/asm/
H A Dsha512-c64xplus.pl25 # it's effectively dominated by SHRU||SHL pairs and you can't schedule
166 || SHL $Ehi,32-14,$S1lo
172 || SHL $Elo,32-14,$t0hi
180 || SHL $Ehi,32-18,$t0lo
188 || SHL $Elo,32-18,$t0hi
196 || SHL $Ehi,64-41,$t0hi
204 || SHL $Elo,64-41,$t0lo
212 || SHL $Ahi,32-28,$S0lo
220 || SHL $Alo,32-28,$t0hi
228 || SHL
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h35 SHL = 0x17, enumerator
92 case SHL: in lanaiAluCodeToString()
112 .Case("sh", SHL) in stringToLanaiAluCode()
134 case ISD::SHL: in isdToLanaiAluCode()
135 return AluCode::SHL; in isdToLanaiAluCode()
H A DLanaiISelLowering.cpp946 Res = DAG.getNode(ISD::SHL, DL, VT, V, in LowerMUL()
960 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32)); in LowerMUL()
1240 assert(Op.getNumOperands() == 3 && "Unexpected SHL!"); in LowerSHL_PARTS()
1264 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerSHL_PARTS()
1268 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerSHL_PARTS()
1276 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerSHL_PARTS()
1315 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32); in LowerSRL_PARTS()
/third_party/node/deps/openssl/openssl/crypto/modes/asm/
H A Dghash-c64xplus.pl73 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
74 SHL $FF000000,24,$FF000000 ; upper byte mask
101 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
103 SHL $FF000000,24,$FF000000 ; upper byte mask
140 || ADD $x1,$x1,$xib ; SHL $x1,1,$xib
141 || SHL $x1,1,$xia
176 || SWAP2.L $H01y,$H1y ; ; SHL $H01y,16,$H1y
177 || SHL $x0,1,$xib
178 || SHL $x0,1,$xia
181 || SHL
[all...]
/third_party/openssl/crypto/modes/asm/
H A Dghash-c64xplus.pl73 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
74 SHL $FF000000,24,$FF000000 ; upper byte mask
101 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
103 SHL $FF000000,24,$FF000000 ; upper byte mask
140 || ADD $x1,$x1,$xib ; SHL $x1,1,$xib
141 || SHL $x1,1,$xia
176 || SWAP2.L $H01y,$H1y ; ; SHL $H01y,16,$H1y
177 || SHL $x0,1,$xib
178 || SHL $x0,1,$xia
181 || SHL
[all...]
/third_party/lzma/Asm/x86/
H A DLzmaDecOpt.asm61 PMULT equ (1 SHL PSHIFT)
62 PMULT_HALF equ (1 SHL (PSHIFT - 1))
63 PMULT_2 equ (1 SHL (PSHIFT + 1))
65 kMatchSpecLen_Error_Data equ (1 SHL 9)
146 kBitModelTotal equ (1 SHL kNumBitModelTotalBits)
148 kBitModelOffset equ ((1 SHL kNumMoveBits) - 1)
149 kTopValue equ (1 SHL 24)
453 kNumPosStatesMax equ (1 SHL kNumPosBitsMax)
456 kLenNumLowSymbols equ (1 SHL kLenNumLowBits)
458 kLenNumHighSymbols equ (1 SHL kLenNumHighBit
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp603 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL) in SelectSHL()
884 case ISD::SHL: return SelectSHL(N); in Select()
1046 if (T1.getOpcode() != ISD::SHL) in ppAddrReorderAddShl()
1071 SDValue NewShl = DAG.getNode(ISD::SHL, DL, VT, NewAdd, C); in ppAddrReorderAddShl()
1147 SDValue NewShl = DAG.getNode(ISD::SHL, dl, VT, NewSrl, DC); in ppAddrRewriteAndSrl()
1616 case ISD::SHL: in isOpcodeHandled()
1725 /// Search for a SHL(x, [<=MaxAmount]) subtree in the queue, return the one of
1743 if (Val.getOpcode() != ISD::SHL || in findSHL()
1810 if (Val.getOpcode() == ISD::SHL) { in getPowerOf2Factor()
1829 } else if (V.getOpcode() == ISD::SHL) { in willShiftRightEliminate()
2122 WeightedLeaf SHL = Leaves.findSHL(31); balanceSubTree() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. in getArithmeticInstrCost()
451 { ISD::SHL, MVT::v16i16, 1 }, // psllw. in getArithmeticInstrCost()
466 { ISD::SHL, MVT::v8i16, 1 }, // psllw. in getArithmeticInstrCost()
467 { ISD::SHL, MVT::v4i32, 1 }, // pslld in getArithmeticInstrCost()
468 { ISD::SHL, MVT::v2i64, 1 }, // psllq. in getArithmeticInstrCost()
498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw in getArithmeticInstrCost()
502 { ISD::SHL, MV in getArithmeticInstrCost()
[all...]
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_gs_visitor.cpp363 inst = emit(SHL(dst_reg(channel_mask), one, channel)); in emit_control_data_bits()
407 emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u))); in set_stream_control_data_bits()
409 /* Note: we're relying on the fact that the GEN SHL instruction only pays in set_stream_control_data_bits()
415 emit(SHL(dst_reg(mask), sid, shift_count)); in set_stream_control_data_bits()
555 /* Note: we're relying on the fact that the GEN SHL instruction only pays in gs_end_primitive()
560 emit(SHL(dst_reg(mask), one, prev_count)); in gs_end_primitive()
H A Dbrw_mesh.cpp989 bld8.SHL(mask, one, mask); in emit_urb_indirect_writes()
990 bld8.SHL(mask, mask, brw_imm_ud(16)); in emit_urb_indirect_writes()
1077 ubld8.SHL(seq_ud, seq_ud, brw_imm_ud(2)); in emit_urb_indirect_reads()
1097 bld8.SHL(comp, comp, brw_imm_ud(ffs(REG_SIZE) - 1)); in emit_urb_indirect_reads()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h26 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp172 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, in addIPMSequence() local
174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence()
/third_party/node/deps/v8/src/parsing/
H A Dtoken.h40 E(T, SHL, "<<", 11) \
319 static bool IsShiftOp(Value op) { return base::IsInRange(op, SHL, SHR); } in IsShiftOp()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp86 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; in PromoteIntegerResult()
668 // 2. SHL by M-N in PromoteIntRes_ADDSUBSAT()
711 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
713 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
772 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, in PromoteIntRes_MULFIX()
949 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SHL()
1211 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, in PromoteIntRes_VAARG()
1290 case ISD::SHL: in PromoteIntegerOperand()
1446 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, in PromoteIntOp_BUILD_PAIR()
1895 case ISD::SHL in ExpandIntegerResult()
[all...]
H A DLegalizeVectorOps.cpp385 case ISD::SHL: in LegalizeOp()
799 DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
818 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); in ExpandLoad()
1056 // Make sure that the SRA and SHL instructions are available. in ExpandSEXTINREG()
1058 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) in ExpandSEXTINREG()
1068 SDValue Op = DAG.getNode(ISD::SHL, DL, VT, Node->getOperand(0), ShiftSz); in ExpandSEXTINREG()
1127 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1221 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) && in ExpandBITREVERSE()
1238 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBITREVERSE()
1357 // Notice that we can also use SHL in ExpandUINT_TO_FLOAT()
[all...]
/third_party/node/deps/v8/src/asmjs/
H A Dasm-names.h92 V("<<", SHL) \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp814 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
816 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
818 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
849 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
850 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1289 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1293 SDValue Mask = DAG.getNode(ISD::SHL, D in LowerSTORE()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp399 case ISD::SHL: in getShiftTypeForNode()
410 /// Determine whether it is worth it to fold SHL into the addressing
413 assert(V.getOpcode() == ISD::SHL && "invalid opcode"); in isWorthFoldingSHL()
442 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL && in isWorthFolding()
448 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS)) in isWorthFolding()
450 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS)) in isWorthFolding()
690 if (N.getOpcode() == ISD::SHL) { in SelectArithExtendedRegister()
918 /// Check if the given SHL node (\p N), can be used to form an
923 assert(N.getOpcode() == ISD::SHL && "Invalid opcode."); in SelectExtendedSHL()
980 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL in SelectAddrModeWRO()
[all...]
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qpu.h207 A_ALU2(SHL)
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_opcode_tmp.h112 OP12(SHL)
/third_party/pulseaudio/speex/libspeexdsp/
H A Darch.h174 #define SHL(a,shift) (a) macro

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