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Searched refs:SDC1 (Results 1 - 13 of 13) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp239 case Mips::SDC1: in isBasePlusOffsetMemoryAccess()
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeMIPS_32.c152 ins = SDC1 | S(SLJIT_SP) | FT(float_arg_count) | IMM(*offsets_ptr); in call_with_args()
H A DsljitNativeMIPS_common.c264 #define SDC1 (HI(61)) macro
889 FAIL_IF(push_inst(compiler, SDC1 | base | FT(i) | IMM(offset), MOVABLE_INS)); in sljit_emit_enter()
894 FAIL_IF(push_inst(compiler, SDC1 | base | FT(i) | IMM(offset), MOVABLE_INS)); in sljit_emit_enter()
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dinstruction-scheduler-mips64.cc547 SDC1 = 1, enumerator
887 int Sdc1Latency() { return AdjustBaseAndOffsetLatency() + Latency::SDC1; } in Sdc1Latency()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
269 Opc = Mips::SDC1; in storeRegToStack()
H A DMipsInstructionSelector.cpp226 return isStore ? Mips::SDC1 : Mips::LDC1; in selectLoadStoreOpCode()
H A DMipsFastISel.cpp837 Opc = Mips::SDC1; in emitStore()
/third_party/node/deps/v8/src/codegen/mips64/
H A Dconstants-mips64.h489 SDC1 = ((7U << 3) + 5) << kOpcodeShift,
1323 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
H A Dassembler-mips64.cc2675 GenInstrImmediate(SDC1, src.rm(), fs, src.offset_); in sdc1()
/third_party/node/deps/v8/src/codegen/mips/
H A Dconstants-mips.h493 SDC1 = ((7U << 3) + 5) << kOpcodeShift,
1271 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dinstruction-scheduler-mips.cc521 SDC1 = 1, enumerator
/third_party/node/deps/v8/src/execution/mips64/
H A Dsimulator-mips64.cc7138 case SDC1:
/third_party/node/deps/v8/src/execution/mips/
H A Dsimulator-mips.cc6764 case SDC1:

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