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Searched refs:S32 (Results 1 - 25 of 26) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp175 const LLT S32 = LLT::scalar(32);
236 S32, S64
240 S32, S64, S16
244 S32, S64, S16, V2S16
248 setAction({G_BRCOND, S32}, Legal); // SCC branches
253 .legalFor({S32, S64, V2S16, V4S16, S1, S128, S256})
258 .clampScalar(0, S32, S256)
260 .clampMaxNumElements(0, S32, 16)
266 .legalFor({S32, S16})
267 .clampScalar(0, S16, S32)
[all...]
H A DAMDGPURegisterBankInfo.cpp71 const LLT S32 = LLT::scalar(32); in applyBank() local
73 assert(MRI.getType(DstReg) == S32); in applyBank()
79 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank()
80 auto False = B.buildConstant(S32, 0); in applyBank()
882 LLT S32 = LLT::scalar(32); in executeInWaterfallLoop() local
909 Register CurrentLaneOpRegLo = MRI.createGenericVirtualRegister(S32); in executeInWaterfallLoop()
910 Register CurrentLaneOpRegHi = MRI.createGenericVirtualRegister(S32); in executeInWaterfallLoop()
943 CurrentLaneOpReg = MRI.createGenericVirtualRegister(S32); in executeInWaterfallLoop()
1276 const LLT S32 = LLT::scalar(32); in handleD16VData() local
1279 return B.buildMerge(LLT::vector(NumElts, S32), WideReg in handleD16VData()
1302 const LLT S32 = LLT::scalar(32); splitBufferOffsets() local
1480 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
1543 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
1575 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
1627 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
1753 LLT S32 = LLT::scalar(32); applyMappingImpl() local
1791 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
1889 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
1978 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
2057 const LLT S32 = LLT::scalar(32); applyMappingImpl() local
[all...]
H A DSIISelLowering.cpp1627 const LLT S32 = LLT::scalar(32); in allocateSpecialEntryInputVGPRs() local
1632 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32); in allocateSpecialEntryInputVGPRs()
1640 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32); in allocateSpecialEntryInputVGPRs()
1648 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32); in allocateSpecialEntryInputVGPRs()
/third_party/typescript/tests/baselines/reference/
H A DcontrolFlowSelfReferentialLoop.js26 var S31=4, S32=11, S33=16, S34=23;
68 d=HH(d,a,b,c,x[k+8], S32,0x8771F681);
72 d=HH(d,a,b,c,x[k+4], S32,0x4BDECFA9);
76 d=HH(d,a,b,c,x[k+0], S32,0xEAA127FA);
80 d=HH(d,a,b,c,x[k+12],S32,0xE6DB99E5);
148 var S31 = 4, S32 = 11, S33 = 16, S34 = 23;
193 d = HH(d, a, b, c, x[k + 8], S32, 0x8771F681);
197 d = HH(d, a, b, c, x[k + 4], S32, 0x4BDECFA9);
201 d = HH(d, a, b, c, x[k + 0], S32, 0xEAA127FA);
205 d = HH(d, a, b, c, x[k + 12], S32,
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIFlagsSection.cpp25 case FpABIKind::S32: in getFpABIValue()
41 case FpABIKind::S32: in getFpABIString()
H A DMipsABIFlagsSection.h23 enum class FpABIKind { ANY, XX, S32, S64, SOFT }; member in llvm::MipsABIFlagsSection::FpABIKind
188 FpABI = FpABIKind::S32; in setFpAbiFromPredicates()
/third_party/skia/third_party/externals/dng_sdk/source/
H A Ddng_fingerprint.cpp471 S32 = 11, in MD5Transform() enumerator
549 HH (d, a, b, c, x[ 8], S32, 0x8771f681); /* 34 */ in MD5Transform()
553 HH (d, a, b, c, x[ 4], S32, 0x4bdecfa9); /* 38 */ in MD5Transform()
557 HH (d, a, b, c, x[ 0], S32, 0xeaa127fa); /* 42 */ in MD5Transform()
561 HH (d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */ in MD5Transform()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp3843 const LLT S32 = LLT::scalar(32); in lowerU64ToF32BitOps() local
3846 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); in lowerU64ToF32BitOps()
3858 auto Zero32 = MIRBuilder.buildConstant(S32, 0); in lowerU64ToF32BitOps()
3861 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); in lowerU64ToF32BitOps()
3863 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); in lowerU64ToF32BitOps()
3864 auto Sub = MIRBuilder.buildSub(S32, K, LZ); in lowerU64ToF32BitOps()
3867 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); in lowerU64ToF32BitOps()
3878 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); in lowerU64ToF32BitOps()
3879 auto V = MIRBuilder.buildOr(S32, Shl in lowerU64ToF32BitOps()
3931 const LLT S32 = LLT::scalar(32); lowerSITOFP() local
3976 const LLT S32 = LLT::scalar(32); lowerFPTOUI() local
[all...]
/third_party/lz4/programs/
H A Dutil.h67 typedef int32_t S32; typedef
75 typedef signed int S32; typedef
/third_party/mesa3d/src/nouveau/codegen/lib/
H A Dgf100.asm41 // DIV S32, like DIV U32 after taking ABS(inputs)
H A Dgm107.asm51 // DIV S32, like DIV U32 after taking ABS(inputs)
H A Dgk110.asm45 // DIV S32, like DIV U32 after taking ABS(inputs)
H A Dgk104.asm45 // DIV S32, like DIV U32 after taking ABS(inputs)
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir_emit.c60 #define IOPC(nir, op, src, cond) OPCT(nir, op, src, cond, S32)
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.cc126 case S32: in Dt_L_imm6_1()
167 case S32: in Dt_L_imm6_2()
248 case S32: in Dt_imm6_1()
285 case S32: in Dt_imm6_2()
347 case S32: in Dt_imm6_4()
375 case S32: in Dt_op_U_size_1()
435 case S32: in Dt_op_size_2()
462 case S32: in Dt_op_size_3()
495 case S32: in Dt_U_imm3H_1()
653 if ((dt1.GetValue() == F32) && (dt2.GetValue() == S32)) { in Dt_op_1()
[all...]
H A Dinstructions-aarch32.cc461 case S32: in GetName()
H A Ddisasm-aarch32.cc112 return S32; in Dt_L_imm6_1_Decode()
133 if (type_value == 0x1) return S32; in Dt_L_imm6_2_Decode()
177 return S32; in Dt_imm6_1_Decode()
196 if (type_value == 0x1) return S32; in Dt_imm6_2_Decode()
232 return S32; in Dt_imm6_4_Decode()
247 return S32; in Dt_op_U_size_1_Decode()
283 return S32; in Dt_op_size_2_Decode()
299 return S32; in Dt_op_size_3_Decode()
319 return S32; in Dt_U_imm3H_1_Decode()
408 return S32; in Dt_op_1_Decode1()
23922 S32, DecodeT32() local
23934 S32, DecodeT32() local
24268 S32, DecodeT32() local
24280 S32, DecodeT32() local
[all...]
H A Dinstructions-aarch32.h266 S32 = kDataTypeS | 32,
/third_party/protobuf/src/google/protobuf/stubs/
H A Dstructurally_valid.cc107 #define S32 (kExitReplace32) macro
369 #undef S32 macro
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.cc2963 enum VFPType { S32, U32, F32, F64 }; enumerator
2967 case S32: in IsSignedVFPType()
2978 case S32: in IsIntegerVFPType()
3058 emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond)); in vcvt_f64_s32()
3063 emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond)); in vcvt_f32_s32()
3079 emit(EncodeVCVT(S32, dst.code(), F32, src.code(), mode, cond)); in vcvt_s32_f32()
3090 emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); in vcvt_s32_f64()
4002 DCHECK(dst_type == S32 || dst_type == U32); in EncodeNeonVCVT()
4005 DCHECK(src_type == S32 || src_type == U32); in EncodeNeonVCVT()
4017 emit(EncodeNeonVCVT(F32, dst, S32, sr in vcvt_f32_s32()
[all...]
/third_party/lz4/lib/
H A Dlz4frame.c173 typedef int32_t S32; typedef
179 typedef signed int S32; typedef
H A Dlz4.c305 typedef int32_t S32; typedef
315 typedef signed int S32; typedef
/third_party/vk-gl-cts/framework/common/
H A DtcuTexture.cpp1301 #define S32(OFFS, COUNT) signExtend(U32(OFFS, COUNT), (COUNT)) in getPixelInt() macro
1321 case TextureFormat::SIGNED_INT_1010102_REV: return swizzleGe(IVec4(S32( 0, 10), S32(10, 10), S32(20, 10), S32(30, 2)), m_format.order, TextureFormat::RGBA); in getPixelInt()
1330 #undef S32 in getPixelInt() macro
/third_party/ffmpeg/libavformat/
H A Davisynth.c770 st->codecpar->codec_id = PCM(S32); in avisynth_create_stream_audio()
/third_party/alsa-lib/src/pcm/
H A Dpcm.c1992 FORMAT(S32),

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