Home
last modified time | relevance | path

Searched refs:Rm (Results 1 - 22 of 22) sorted by relevance

/third_party/vixl/src/aarch64/
H A Dassembler-sve-aarch64.cc83 Rm(addr.GetVectorOffset())); in adr()
136 Emit(AND_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in and_()
145 Emit(BIC_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in bic()
154 Emit(EOR_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in eor()
163 Emit(ORR_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in orr()
404 Emit(ASR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm)); in asr()
421 Emit(LSL_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm)); in lsl()
438 Emit(LSR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm)); in lsr()
974 Emit(FADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm)); in fadd()
988 Emit(FMUL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(z in fmul()
[all...]
H A Dassembler-aarch64.cc323 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
648 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
657 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
666 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
675 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
720 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.GetSizeInBits()) | Rn(rn) | in extr()
796 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
821 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd)); in DataProcessing3Source()
830 Emit(SF(wm) | Rm(wm) | CRC32B | Rn(wn) | Rd(wd)); in crc32b()
839 Emit(SF(wm) | Rm(w in crc32h()
[all...]
H A Dconstants-aarch64.h78 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \
H A Dassembler-aarch64.h7153 return Rm(rm); in RmNot31()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1453 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1458 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1490 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1495 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
1829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
1891 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1933 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
1959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
1978 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
2011 if (type && Rm in DecodeAddrMode3Instruction()
2197 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeQADDInstruction() local
2475 unsigned Rm = fieldFromInstruction(Insn, 8, 4); DecodeSMLAInstruction() local
2503 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeTSTInstruction() local
2668 unsigned Rm = fieldFromInstruction(Val, 0, 4); DecodeAddrMode6Operand() local
2690 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLDInstruction() local
3017 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVSTInstruction() local
3285 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD1DupInstruction() local
3332 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD2DupInstruction() local
3380 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD3DupInstruction() local
3415 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD4DupInstruction() local
3566 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVSHLMaxInstruction() local
3611 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeTBLInstruction() local
3692 unsigned Rm = fieldFromInstruction(Val, 3, 3); DecodeThumbAddrModeRR() local
3739 unsigned Rm = fieldFromInstruction(Val, 2, 4); DecodeT2AddrModeSOReg() local
4398 unsigned Rm = fieldFromInstruction(Insn, 3, 4); DecodeThumbAddSPReg() local
4423 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodePostIdxReg() local
4515 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeThumbTableBranch() local
4829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeLDRPreReg() local
4901 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD1LN() local
4968 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVST1LN() local
5033 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD2LN() local
5100 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVST2LN() local
5163 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD3LN() local
5233 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVST3LN() local
5296 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVLD4LN() local
5377 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeVST4LN() local
5449 unsigned Rm = fieldFromInstruction(Insn, 5, 1); DecodeVMOVSRR() local
5475 unsigned Rm = fieldFromInstruction(Insn, 5, 1); DecodeVMOVRRS() local
5818 unsigned Rm = fieldFromInstruction(Val, 0, 4); DecodeLDR() local
6473 unsigned Rm = fieldFromInstruction(Insn, 12, 4); DecodeMVEOverlappingLongShift() local
6580 unsigned Rm = fieldFromInstruction(Insn, 0, 4); DecodeMVEVCMP() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.cpp305 // mmmm is the index register Rm, iiiii is the shift amount, ss is the shift
318 // Value=ssss0tt1mmmm where mmmm=Rm, tt is an encoded ShiftKind, and ssss=Rms.
333 // tt=Shift, and mmmm=Rm.
334 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift,
338 return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
341 // Encodes mmmmtt01ssss for data-processing operands where mmmm=Rm, ssss=Rs, and
343 IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
346 (Rm << kRmShift);
389 IValueT Rm;
390 if (encodeOperand(FlexReg->getReg(), Rm, WantGPReg
[all...]
H A DIceAssemblerX8664.h958 // for Reg and Rm because they could be of different types (e.g., in
959 // mov[sz]x instructions.) If Addr is not nullptr, then Rm is ignored, and
964 const RmType Rm, const AsmAddress *Addr = nullptr) { in assembleAndEmitRex()
972 : (Rm & 0x08) ? AsmOperand::RexB in assembleAndEmitRex()
978 (Addr == nullptr && is8BitRegisterRequiringRex(TyRm, Rm))) { in assembleAndEmitRex()
986 void emitRexRB(const Type Ty, const RegType Reg, const RmType Rm) { in emitRexRB() argument
987 assembleAndEmitRex(Ty, Reg, Ty, Rm); in emitRexRB()
992 const RmType Rm) { in emitRexRB()
993 assembleAndEmitRex(TyReg, Reg, TyRm, Rm); in emitRexRB()
999 template <typename RmType> void emitRexB(const Type Ty, const RmType Rm) { in emitRexB() argument
963 assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm, const RmType Rm, const AsmAddress *Addr = nullptr) assembleAndEmitRex() argument
991 emitRexRB(const Type TyReg, const RegType Reg, const Type TyRm, const RmType Rm) emitRexRB() argument
[all...]
H A DIceAssemblerARM32.h199 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
743 // xxxxxxxxxxxx0000xxxxxxxx0000=Opcode, dddd=Rd, and mmmm=Rm.
783 // mmmmm=Rm, tttt=NumDRegs, ElmtSize in {8, 16, 32, 64) and defines ss, and
785 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
790 // mmmmm=Rm, ElmtSize in {8, 16, 32) and defines ss, and aa=Align.
791 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
795 // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
797 IValueT Rm);
811 // mmmm=Rm, ssss=Rs, f=SetFlags and xxxxxxx=Opcode.
813 IValueT Rm, IValue
[all...]
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc92 void FormatNeonMemory(int Rn, int align, int Rm);
308 } else if (format[1] == 'm') { // 'rm: Rm register in FormatRegister()
403 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { in FormatNeonMemory() argument
410 if (Rm == 15) { in FormatNeonMemory()
412 } else if (Rm == 13) { in FormatNeonMemory()
416 converter_.NameOfCPURegister(Rm)); in FormatNeonMemory()
749 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
755 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
767 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> in DecodeType01()
2459 int Rm in DecodeAdvancedSIMDElementOrStructureLoadStore() local
[all...]
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc1081 T op2 = reg<T>(instr->Rm()); in AddSubWithCarry()
1166 T op2 = reg<T>(instr->Rm());
1829 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount);
1832 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
1850 uint64_t op2 = ExtendValue(xreg(instr->Rm()), ext, left_shift);
1853 uint32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift);
1871 uint64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount);
1875 uint32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
1927 ConditionalCompareHelper(instr, static_cast<uint64_t>(xreg(instr->Rm())));
1929 ConditionalCompareHelper(instr, static_cast<uint32_t>(wreg(instr->Rm())));
[all...]
/third_party/node/deps/v8/src/diagnostics/arm64/
H A Ddisasm-arm64.h63 return (instr->Rm() == kZeroRegCode); in RmIsZROrSP()
H A Ddisasm-arm64.cc100 const char* form = "'Rd, 'Rn, 'Rm'NDP"; in VisitAddSubShifted()
101 const char* form_cmp = "'Rn, 'Rm'NDP"; in VisitAddSubShifted()
102 const char* form_neg = "'Rd, 'Rm'NDP"; in VisitAddSubShifted()
190 const char* form = "'Rd, 'Rn, 'Rm"; in VisitAddSubWithCarry()
191 const char* form_neg = "'Rd, 'Rm"; in VisitAddSubWithCarry()
304 const char* form = "'Rd, 'Rn, 'Rm'NLo"; in VisitLogicalShifted()
332 form = "'Rn, 'Rm'NLo"; in VisitLogicalShifted()
341 form = "'Rd, 'Rm"; in VisitLogicalShifted()
350 form = "'Rd, 'Rm'NLo"; in VisitLogicalShifted()
363 const char* form = "'Rn, 'Rm, 'INzc in VisitConditionalCompareRegister()
[all...]
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.cc957 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
964 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
971 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
978 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1011 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.SizeInBits()) | Rn(rn) | in extr()
1067 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
1083 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd)); in DataProcessing3Source()
1157 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd)); in sdiv()
1164 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd)); in udiv()
1447 Emit(format | op | Rm(v in NEON3DifferentL()
[all...]
H A Dinstructions-arm64.h405 return (Mask(LogicalShiftedMask) == ORR_x) && (Rd() == Rm()) && (Rd() == n); in IsNop()
H A Dassembler-arm64.h2117 static Instr Rm(CPURegister rm) {
2125 return Rm(rm);
H A Dconstants-arm64.h155 V_(Rm, 20, 16, Bits) /* Second source register. */ \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp938 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
966 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
987 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1509 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1523 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1529 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1535 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1541 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1547 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1553 DecodeGPR64RegisterClass(Inst, Rm, Add in DecodeAddSubERegInstruction()
[all...]
/third_party/ffmpeg/libavcodec/arm/
H A Dhpeldsp_arm.S53 @ Rd = (Rn | Rm) - (((Rn ^ Rm) & ~0x01010101) >> 1)
67 @ Rd = (Rn & Rm) - (((Rn ^ Rm) & ~0x01010101) >> 1)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3375 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3376 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3382 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3383 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3412 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3413 if (!Rm) in getNumMicroOpsSwiftLdSt()
3415 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3424 Register Rm = MI.getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
3425 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3443 Register Rm in getNumMicroOpsSwiftLdSt() local
3463 Register Rm = MI.getOperand(3).getReg(); getNumMicroOpsSwiftLdSt() local
3471 Register Rm = MI.getOperand(3).getReg(); getNumMicroOpsSwiftLdSt() local
3489 Register Rm = MI.getOperand(4).getReg(); getNumMicroOpsSwiftLdSt() local
3503 Register Rm = MI.getOperand(4).getReg(); getNumMicroOpsSwiftLdSt() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp933 // [Rn, Rm] in getThumbAddrModeRegRegOpValue()
934 // {5-3} = Rm in getThumbAddrModeRegRegOpValue()
939 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue() local
940 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1257 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1270 // {3-0} = Rm
1274 uint32_t Binary = Rm;
1287 // {13} 1 == imm12, 0 == Rm
1289 // {11-0} imm12/Rm
1296 // if reg +/- reg, Rm wil
[all...]
/third_party/node/deps/v8/src/execution/arm/
H A Dsimulator-arm.h339 void AdvancedSIMDElementOrStructureLoadStoreWriteback(int Rn, int Rm,
H A Dsimulator-arm.cc85 void Simulator::AdvancedSIMDElementOrStructureLoadStoreWriteback(int Rn, int Rm, in AdvancedSIMDElementOrStructureLoadStoreWriteback() argument
87 if (Rm != 15) { in AdvancedSIMDElementOrStructureLoadStoreWriteback()
88 if (Rm == 13) { in AdvancedSIMDElementOrStructureLoadStoreWriteback()
91 set_register(Rn, get_register(Rn) + get_register(Rm)); in AdvancedSIMDElementOrStructureLoadStoreWriteback()
2059 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
5764 int Rm = instr->VmValue(); in DecodeAdvancedSIMDLoadStoreMultipleStructures() local
5807 AdvancedSIMDElementOrStructureLoadStoreWriteback(Rn, Rm, 8 * regs); in DecodeAdvancedSIMDLoadStoreMultipleStructures()
5817 int Rm = instr->VmValue(); in DecodeAdvancedSIMDLoadSingleStructureToAllLanes() local
5853 AdvancedSIMDElementOrStructureLoadStoreWriteback(Rn, Rm, 1 << size); in DecodeAdvancedSIMDLoadSingleStructureToAllLanes()
5866 int Rm in DecodeAdvancedSIMDLoadStoreSingleStructureToOneLane() local
[all...]

Completed in 90 milliseconds