Home
last modified time | relevance | path

Searched refs:ReplaceLane (Results 1 - 16 of 16) sorted by relevance

/third_party/node/deps/v8/src/codegen/arm/
H A Dmacro-assembler-arm.h460 void ReplaceLane(QwNeonRegister dst, QwNeonRegister src, Register src_lane,
462 void ReplaceLane(QwNeonRegister dst, QwNeonRegister src,
464 void ReplaceLane(QwNeonRegister dst, QwNeonRegister src,
H A Dmacro-assembler-arm.cc1119 void TurboAssembler::ReplaceLane(QwNeonRegister dst, QwNeonRegister src, in CallRecordWriteStub() function in v8::internal::TurboAssembler
1132 void TurboAssembler::ReplaceLane(QwNeonRegister dst, QwNeonRegister src, in CallRecordWriteStub() function in v8::internal::TurboAssembler
1139 void TurboAssembler::ReplaceLane(QwNeonRegister dst, QwNeonRegister src, in CallRecordWriteStub() function in v8::internal::TurboAssembler
/third_party/node/deps/v8/src/wasm/
H A Dwasm-opcodes-inl.h273 CASE_SIMDF_OP(ReplaceLane, "replace_lane") in OpcodeName()
278 CASE_SIMDI_OP(ReplaceLane, "replace_lane") in OpcodeName()
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc1827 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2047 __ ReplaceLane(dst, dst, i.InputRegister(1), NeonS32, 1); in AssembleArchInstruction()
2048 __ ReplaceLane(dst, dst, i.InputRegister(1), NeonS32, 3); in AssembleArchInstruction()
2054 __ ReplaceLane(dst, dst, i.InputRegister(2), NeonS32, lane * 2); in AssembleArchInstruction()
2055 __ ReplaceLane(dst, dst, i.InputRegister(3), NeonS32, lane * 2 + 1); in AssembleArchInstruction()
2176 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2323 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2524 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2705 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
H A Dinstruction-selector-arm.cc2768 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
2769 VisitRRIR(this, kArm##Type##ReplaceLane, node); \
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h2479 ReplaceLane(liftoff::GetSimd128Register(dst), in emit_f64x2_replace_lane()
2663 ReplaceLane(liftoff::GetSimd128Register(dst), in emit_f32x4_replace_lane()
2832 ReplaceLane(dst_simd, dst_simd, src.high_gp(), NeonS32, 1); in emit_i64x2_splat()
2833 ReplaceLane(dst_simd, dst_simd, src.high_gp(), NeonS32, 3); in emit_i64x2_splat()
2851 ReplaceLane(dst_simd, src1_simd, src2.low_gp(), NeonS32, imm_lane_idx * 2); in emit_i64x2_replace_lane()
2852 ReplaceLane(dst_simd, dst_simd, src2.high_gp(), NeonS32, in emit_i64x2_replace_lane()
3033 ReplaceLane(liftoff::GetSimd128Register(dst), in emit_i32x4_replace_lane()
3392 ReplaceLane(liftoff::GetSimd128Register(dst),
3526 ReplaceLane(liftoff::GetSimd128Register(dst),
/third_party/node/deps/v8/src/compiler/
H A Dmachine-operator.cc1973 const Operator* MachineOperatorBuilder::Type##ReplaceLane( \
1976 return zone_->New<Operator1<int32_t>>(IrOpcode::k##Type##ReplaceLane, \
/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dinstruction-selector-mips.cc2334 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
2335 VisitRRIR(this, kMips##Type##ReplaceLane, node); \
/third_party/node/deps/v8/src/compiler/backend/ppc/
H A Dinstruction-selector-ppc.cc2411 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
2414 Emit(kPPC_##Type##ReplaceLane, g.DefineSameAsFirst(node), \
/third_party/node/deps/v8/src/compiler/backend/s390/
H A Dinstruction-selector-s390.cc2621 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
2624 Emit(kS390_##Type##ReplaceLane, g.DefineAsRegister(node), \
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dinstruction-selector-mips64.cc3098 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
3099 VisitRRIR(this, kMips64##Type##ReplaceLane, node); \
/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dinstruction-selector-arm64.cc3633 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
3634 VisitRRIR(this, kArm64##T##ReplaceLane | LaneSizeField::encode(LaneSize), \
/third_party/node/deps/v8/src/compiler/backend/loong64/
H A Dinstruction-selector-loong64.cc2842 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
2843 VisitRRIR(this, kLoong64##Type##ReplaceLane, node); \
/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dinstruction-selector-riscv64.cc3071 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
3072 VisitRRIR(this, kRiscv##Type##ReplaceLane, node); \
/third_party/node/deps/v8/src/compiler/backend/x64/
H A Dinstruction-selector-x64.cc3288 void InstructionSelector::Visit##TYPE##ReplaceLane(Node* node) { \
/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dinstruction-selector-ia32.cc2618 void InstructionSelector::Visit##TYPE##ReplaceLane(Node* node) { \

Completed in 75 milliseconds