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Searched refs:Rd (Results 1 - 25 of 29) sorted by relevance

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/third_party/vixl/src/aarch64/
H A Dassembler-sve-aarch64.cc82 Emit(op | msz | Rd(zd) | Rn(addr.GetVectorBase()) | in adr()
93 Emit(op | Rd(zdn) | SVEBitN(bit_n) | SVEImmRotate(imm_r, lane_size) | in SVELogicalImmediate()
136 Emit(AND_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in and_()
145 Emit(BIC_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in bic()
154 Emit(EOR_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in eor()
163 Emit(ORR_z_zz | Rd(zd) | Rn(zn) | Rm(zm)); in orr()
175 Emit(op | tszh | tszl_and_imm | PgLow8(pg) | Rd(zdn)); in SVEBitwiseShiftImmediatePred()
214 Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm)); in asr()
249 Emit(ASRR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm)); in asrr()
289 Emit(op | SVESize(zd) | Rd(z in lsl()
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H A Dassembler-aarch64.cc323 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
449 Emit(ADR | ImmPCRelAddress(imm21) | Rd(xd)); in adr()
460 Emit(ADRP | ImmPCRelAddress(imm21) | Rd(xd)); in adrp()
648 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
657 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
666 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
675 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
687 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd)); in bfm()
698 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd)); in sbfm()
709 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(r in ubfm()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint() argument
160 if (Rd == Ra) in addIntraChainConstraint()
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) { in addIntraChainConstraint()
166 LLVM_DEBUG(dbgs() << "Rd is a physical reg:" in addIntraChainConstraint()
167 << Register::isPhysicalRegister(Rd) << '\n'); in addIntraChainConstraint()
173 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); in addIntraChainConstraint()
186 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint() argument
248 if (Rd != Ra) { in addInterChainConstraint()
250 << " to " << printReg(Rd, TR in addInterChainConstraint()
362 Register Rd = MI.getOperand(0).getReg(); apply() local
372 Register Rd = MI.getOperand(0).getReg(); apply() local
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H A DAArch64PBQPRegAlloc.h30 // parity(Rd) == parity(Ra).
32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2204 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeQADDInstruction()
2422 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2431 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2433 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2446 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2454 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2473 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2482 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres in DecodeSMLAInstruction()
2685 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLDInstruction() local
3012 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVSTInstruction() local
3282 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD1DupInstruction() local
3329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD2DupInstruction() local
3377 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD3DupInstruction() local
3412 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD4DupInstruction() local
3465 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVMOVModImmInstruction() local
3564 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVSHLMaxInstruction() local
3607 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeTBLInstruction() local
4773 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeDoubleRegStore() local
4902 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD1LN() local
4969 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST1LN() local
5034 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD2LN() local
5101 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST2LN() local
5164 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD3LN() local
5234 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST3LN() local
5297 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVLD4LN() local
5378 unsigned Rd = fieldFromInstruction(Insn, 12, 4); DecodeVST4LN() local
5602 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); DecodeT2Adr() local
6623 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); DecodeT2AddSubSPImm() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp845 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
850 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
853 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
936 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
964 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
985 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
998 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1010 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
1015 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
1507 unsigned Rd in DecodeAddSubERegInstruction() local
1564 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeLogicalImmInstruction() local
1595 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeModImmInstruction() local
1634 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeModImmTiedInstruction() local
1651 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeAdrInstruction() local
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5); DecodeAddSubImmShift() local
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/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.cc826 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
957 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
964 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
971 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
978 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
987 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in bfm()
995 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in sbfm()
1003 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in ubfm()
1012 Rd(rd)); in extr()
1067 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(r in ConditionalSelect()
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H A Dinstructions-arm64.h254 // Indicate whether Rd can be the stack pointer or the zero register. This
255 // does not check that the instruction actually has an Rd field.
257 // The following instructions use sp or wsp as Rd: in RdMode()
405 return (Mask(LogicalShiftedMask) == ORR_x) && (Rd() == Rm()) && (Rd() == n); in IsNop()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.cpp675 // cccc00110T00iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd,
797 IValueT Rd, IValueT Imm12,
803 verifyRegNotPcWhenSetFlags(Rd, SetFlags, InstName);
806 assert(Rd < RegARM32::getNumGPRegs());
811 (Rn << kRnShift) | (Rd << kRdShift) | Imm12;
819 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName);
821 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, RuleChecks, InstName);
825 IValueT Rd, IValueT Rn, const Operand *OpSrc1,
837 // xxx{s}<c> <Rd>, <R
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H A DIceAssemblerMIPS32.cpp271 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRtSa() local
275 Opcode |= Rd << 11; in emitRdRtSa()
284 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRsRt() local
290 Opcode |= Rd << 11; in emitRdRsRt()
527 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz"); in clz() local
529 Opcode |= Rd << 11; in clz()
530 Opcode |= Rd << 1 in clz()
657 const IValueT Rd = jalr() local
774 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi"); mfhi() local
781 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mflo"); mflo() local
821 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "pseudo-move"); move() local
840 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf"); movf() local
875 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movt"); movt() local
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H A DIceAssemblerARM32.h715 // s=SetFlags, oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM
718 bool SetFlags, IValueT Rn, IValueT Rd, IValueT imm12,
727 // Same as above, but the value for Rd and Rn have already been converted
743 // xxxxxxxxxxxx0000xxxxxxxx0000=Opcode, dddd=Rd, and mmmm=Rm.
795 // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
796 void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
810 // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
812 void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
816 // dddd=Rd, mmmm=Rm, tt=Shift, and xxxxx is defined by OpSrc1. OpSrc1 defines
825 // nnnn=Rn, dddd=Rd, r
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp325 Register Rd; member
395 OffsetRange getOffsetRange(Register Rd) const;
498 if (ED.Rd.Reg != 0) in operator <<()
499 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); in operator <<()
1126 // Get the allowable deviation from the current value of Rd by checking
1127 // all uses of Rd.
1128 OffsetRange HCE::getOffsetRange(Register Rd) const { in getOffsetRange()
1130 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) { in getOffsetRange()
1134 if (Rd ! in getOffsetRange()
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H A DHexagonFrameLowering.cpp143 // Rd = PS_alloca Rs, A
145 // Rd - address of the allocated space
2391 // Rd = alloca Rs, #A in expandAlloca()
2393 // If Rs and Rd are different registers, use this sequence: in expandAlloca()
2394 // Rd = sub(r29, Rs) in expandAlloca()
2396 // Rd = and(Rd, #-A) ; if necessary in expandAlloca()
2398 // Rd = add(Rd, #CF) ; CF size aligned to at most A in expandAlloca()
2400 // Rd in expandAlloca()
2407 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); expandAlloca() local
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H A DHexagonInstrInfo.cpp1234 Register Rd = Op0.getReg(); in expandPostRAPseudo() local
1242 if (Rd != Rs) in expandPostRAPseudo()
1243 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd) in expandPostRAPseudo()
1244 .addReg(Pu, (Rd == Rt) ? K1 : 0) in expandPostRAPseudo()
1246 if (Rd != Rt) in expandPostRAPseudo()
1247 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd) in expandPostRAPseudo()
3330 // Rd = Rs in getCompoundCandidateGroup()
3337 // Rd = #u6 in getCompoundCandidateGroup()
3367 // Rd=#U6 ; jump #r9:2 in getCompoundCandidateGroup()
3368 // Rd in getCompoundCandidateGroup()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp296 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
298 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); in decodeRVCInstrRdRs2()
306 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
308 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); in decodeRVCInstrRdRs1Rs2()
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc1091 set_reg<T>(instr->Rd(), new_val); in AddSubWithCarry()
1173 set_reg<T>(instr->Rd(), result);
1688 set_reg(instr->Rd(), instr->ImmPCOffsetTarget());
1821 set_reg<T>(instr->Rd(), new_val, instr->RdMode());
1922 set_reg<T>(instr->Rd(), result, instr->RdMode());
2524 unsigned reg_code = instr->Rd();
2539 set_xreg(instr->Rd(), new_xn_val);
2569 set_xreg(instr->Rd(), new_val);
2571 set_wreg(instr->Rd(), static_cast<uint32_t>(new_val));
2576 unsigned dst = instr->Rd();
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/third_party/ffmpeg/libavcodec/
H A Djpeglsenc.c148 int Ra = R(tmp, 0), Rb, Rc = last2, Rd; in ls_encode_line() local
156 Rd = (x >= w - stride) ? R(tmp, x) : R(tmp, x + stride); in ls_encode_line()
157 D0 = Rd - Rb; in ls_encode_line()
H A Djpeglsdec.c236 int Ra, Rb, Rc, Rd; in ls_decode_line() local
249 Rd = (x >= w - stride) ? R(last, x) : R(last, x + stride); in ls_decode_line()
250 D0 = Rd - Rb; in ls_decode_line()
/third_party/node/deps/v8/src/diagnostics/arm64/
H A Ddisasm-arm64.h55 return (instr->Rd() == kZeroRegCode); in RdIsZROrSP()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local
196 switch (Rd) { in DecodeDstAddrMode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1680 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1697 TmpInst.addOperand(Rd); in processInstruction()
1711 if (Value == 0) { // convert to $Rd = $Rs in processInstruction()
1713 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1715 TmpInst.addOperand(Rd); in processInstruction()
1723 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1725 TmpInst.addOperand(Rd); in processInstruction()
1911 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1914 TmpInst.addOperand(Rd); in processInstruction()
/third_party/node/deps/openssl/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2558 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7));
2624 pxor $Rd, $Rd
2654 por $T0d, $Rd
2665 movdqu $Rd, 16*3($val)
2744 pxor $Rd, $Rd
2768 por $T0d, $Rd
2776 movdqu $Rd, 16*3($val)
/third_party/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2558 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7));
2624 pxor $Rd, $Rd
2654 por $T0d, $Rd
2665 movdqu $Rd, 16*3($val)
2744 pxor $Rd, $Rd
2768 por $T0d, $Rd
2776 movdqu $Rd, 16*3($val)
/third_party/ffmpeg/libavcodec/arm/
H A Dhpeldsp_arm.S53 @ Rd = (Rn | Rm) - (((Rn ^ Rm) & ~0x01010101) >> 1)
67 @ Rd = (Rn & Rm) - (((Rn ^ Rm) & ~0x01010101) >> 1)
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc300 } else if (format[1] == 'd') { // 'rd: Rd register in FormatRegister()
742 // The MUL instruction description (A 4.1.33) refers to Rd as being in DecodeType01()
749 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
750 // Rn field to encode the Rd register and the Rd field to encode in DecodeType01()
755 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the in DecodeType01()
756 // Rn field to encode the Rd register and the Rd field to encode in DecodeType01()
764 // and Rd fields as follows: in DecodeType01()
765 // RdLo == Rd fiel in DecodeType01()
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