/third_party/musl/libc-test/src/math/ |
H A D | fenv.c | 202 T(RZ, 0x1p+0, 0x1p-52, 0x1.0000000000001p+0, 0x0p+0, 0) 203 T(RZ, 0x1p+0, 0x1p-53, 0x1p+0, -0x1p-1, INEXACT) 204 T(RZ, 0x1p+0, 0x1.01p-53, 0x1p+0, -0x1.01p-1, INEXACT) 205 T(RZ, 0x1p+0, -0x1p-54, 0x1.fffffffffffffp-1, -0x1p-1, INEXACT) 206 T(RZ, 0x1p+0, -0x1.01p-54, 0x1.fffffffffffffp-1, -0x1.fep-2, INEXACT) 207 T(RZ, -0x1p+0, -0x1p-53, -0x1p+0, 0x1p-1, INEXACT) 208 T(RZ, -0x1p+0, -0x1.01p-53, -0x1p+0, 0x1.01p-1, INEXACT) 209 T(RZ, -0x1p+0, 0x1p-54, -0x1.fffffffffffffp-1, 0x1p-1, INEXACT) 210 T(RZ, -0x1p+0, 0x1.01p-54, -0x1.fffffffffffffp-1, 0x1.fep-2, INEXACT)
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/third_party/ltp/tools/sparse/sparse-src/validation/ |
H A D | enum-bitwise.c | 7 RZ = (__force bits) 0, enumerator 12 _Static_assert([typeof(RZ)] == [bits], "RZ");
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/third_party/musl/libc-test/src/math/gen/ |
H A D | gen.h | 6 #undef RZ macro 10 #define RZ FE_TOWARDZERO macro
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H A D | util.c | 143 case RZ: return "RZ"; in rstr() 154 else if (strcmp(s, "RZ") == 0) in rconv() 155 *r = RZ; in rconv()
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H A D | mp.c | 10 case RZ: return MPFR_RNDZ; in rmap() 133 // happens in RU,RD,RZ modes when y is finite but outside the domain in genf() 187 // happens in RU,RD,RZ modes when y is finite but outside the domain in gend() 242 // happens in RU,RD,RZ modes when y is finite but outside the domain in genl()
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/third_party/musl/libc-test/src/common/ |
H A D | mtest.h | 6 #undef RZ macro 15 #define RZ FE_TOWARDZERO macro 17 #define RZ -1 macro
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H A D | mtest.c | 142 case RZ: return "RZ"; in rstr()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
H A D | NVPTX.h | 119 RZ, enumerator
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/third_party/node/deps/v8/src/codegen/arm/ |
H A D | constants-arm.h | 374 RZ = 3 << 22, // Round towards zero. enumerator 380 kRoundToZero = RZ
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/third_party/node/deps/v8/src/codegen/loong64/ |
H A D | constants-loong64.h | 663 RZ = 0b01 << kFPURoundingModeShift, // Round towards zero. 669 kRoundToZero = RZ, 676 mode_trunc = RZ
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/MCTargetDesc/ |
H A D | NVPTXInstPrinter.cpp | 133 case NVPTX::PTXCvtMode::RZ: in printCvtMode()
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/third_party/node/deps/v8/src/codegen/mips64/ |
H A D | constants-mips64.h | 1204 RZ = 1 << 0, // Round towards zero. 1210 kRoundToZero = RZ, 1217 mode_trunc = RZ
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/third_party/node/deps/v8/src/codegen/mips/ |
H A D | constants-mips.h | 1155 RZ = 1 << 0, // Round towards zero. 1161 kRoundToZero = RZ, 1168 mode_trunc = RZ
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 704 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) 707 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
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/third_party/node/deps/v8/src/execution/arm/ |
H A D | simulator-arm.cc | 3653 DCHECK((mode == RN) || (mode == RM) || (mode == RZ)); in get_inv_op_vfp_flag() 3674 case RZ: in get_inv_op_vfp_flag() 3744 case RZ: in ConvertDoubleToInt() 3780 VFPRoundingMode mode = (instr->Bit(7) != 1) ? FPSCR_rounding_mode_ : RZ; in DecodeVCVTBetweenFloatingPointAndInteger() 3781 DCHECK((mode == RM) || (mode == RZ) || (mode == RN)); in DecodeVCVTBetweenFloatingPointAndInteger() 4891 ConvertDoubleToInt(bit_cast<float>(q_data[i]), false, RZ)); in DecodeAdvancedSIMDTwoOrThreeRegisters() 4896 ConvertDoubleToInt(bit_cast<float>(q_data[i]), true, RZ)); in DecodeAdvancedSIMDTwoOrThreeRegisters()
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/third_party/node/deps/v8/src/codegen/ppc/ |
H A D | constants-ppc.h | 2871 RZ = 1, // Round towards zero. enumerator 2877 kRoundToZero = RZ,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/ |
H A D | AddressSanitizer.cpp | 2274 // MinRZ <= RZ <= kMaxGlobalRedzone in InstrumentGlobals() 2275 // and trying to make RZ to be ~ 1/4 of SizeInBytes. in InstrumentGlobals() 2276 uint64_t RZ = std::max( in InstrumentGlobals() local 2278 uint64_t RightRedzoneSize = RZ; in InstrumentGlobals()
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