Home
last modified time | relevance | path

Searched refs:RRX (Results 1 - 12 of 12) sorted by relevance

/third_party/vixl/src/aarch32/
H A Dinstructions-aarch32.cc54 case RRX: in IsValidAmount()
430 case RRX: in GetName()
594 if (amount_value == 0) SetType(RRX); in ImmediateShiftOperand()
735 case RRX: in AmountEncodingValue()
H A Doperands-aarch32.h72 // <shift> is RRX
99 case RRX: in Operand()
710 // <shift> is RRX, applied to value from rm
730 // <shift> is RRX, applied to value from rm
838 // Disallow any zero shift other than RRX #0 and LSL #0 . in CheckShift()
857 case RRX: in CheckShift()
H A Dinstructions-aarch32.h1058 enum ShiftType { LSL = 0x0, LSR = 0x1, ASR = 0x2, ROR = 0x3, RRX = 0x4 };
1073 bool IsRRX() const { return shift_ == RRX; }
1109 case RRX:
H A Dmacro-assembler-aarch32.cc728 case RRX:
729 // A RegisterShiftedRegister operand cannot have a shift of type RRX.
846 case RRX:
847 // A RegisterShiftedRegister operand cannot have a shift of type RRX.
1042 case RRX: in Delegate()
1043 // A RegisterShiftedRegister operand cannot have a shift of type RRX. in Delegate()
H A Ddisasm-aarch32.cc18161 // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, RRX ; T2 in DecodeT32()
18166 Operand(Register(rm), RRX)); in DecodeT32() local
18227 // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, RRX ; T2 in DecodeT32()
18232 Operand(Register(rm), RRX)); in DecodeT32() local
18295 // RRX{<c>}{<q>} {<Rd>}, <Rm> ; T3 in DecodeT32()
18487 // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, RRX ; T2 in DecodeT32()
18492 Operand(Register(rm), RRX)); in DecodeT32() local
18560 // MVN{<c>}{<q>} <Rd>, <Rm>, RRX ; T2 in DecodeT32()
18564 Operand(Register(rm), RRX)); in DecodeT32() local
18625 // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, RRX ; T in DecodeT32()
18629 Operand(Register(rm), RRX)); DecodeT32() local
18686 Operand(Register(rm), RRX)); DecodeT32() local
18748 Operand(Register(rm), RRX)); DecodeT32() local
18819 Operand(Register(rm), RRX)); DecodeT32() local
19066 Operand(Register(rm), RRX)); DecodeT32() local
19138 Operand(Register(rm), RRX)); DecodeT32() local
19203 Operand(Register(rm), RRX)); DecodeT32() local
19259 Operand(Register(rm), RRX)); DecodeT32() local
19378 Operand(Register(rm), RRX)); DecodeT32() local
19425 Operand(Register(rm), RRX)); DecodeT32() local
19507 Operand(Register(rm), RRX)); DecodeT32() local
19573 Operand(Register(rm), RRX)); DecodeT32() local
19657 Operand(Register(rm), RRX)); DecodeT32() local
19723 Operand(Register(rm), RRX)); DecodeT32() local
19799 Operand(Register(rm), RRX)); DecodeT32() local
19863 Operand(Register(rm), RRX)); DecodeT32() local
19914 Operand(Register(rm), RRX)); DecodeT32() local
19990 Operand(Register(rm), RRX)); DecodeT32() local
20056 Operand(Register(rm), RRX)); DecodeT32() local
20133 Operand(Register(rm), RRX)); DecodeT32() local
20198 Operand(Register(rm), RRX)); DecodeT32() local
20269 Operand(Register(rm), RRX)); DecodeT32() local
20326 Operand(Register(rm), RRX)); DecodeT32() local
20388 Operand(Register(rm), RRX)); DecodeT32() local
20439 Operand(Register(rm), RRX)); DecodeT32() local
20515 Operand(Register(rm), RRX)); DecodeT32() local
[all...]
/third_party/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc248 __ Adc(r9, r2, Operand(r3, RRX)); in TEST()
276 __ Adc(r10, r2, Operand(r3, RRX)); in TEST()
369 // Clear the C flag, forcing RRX to insert 0 in r1's most significant bit. in TEST()
371 __ Adcs(r3, r2, Operand(r1, RRX)); in TEST()
384 // Set the C flag, forcing RRX to insert 1 in r1's most significant bit. in TEST()
386 __ Adcs(r3, r2, Operand(r1, RRX)); in TEST()
487 __ Add(r9, r3, Operand(r1, RRX)); in TEST()
491 __ Add(r10, r3, Operand(r1, RRX)); in TEST()
524 __ And(r9, r1, Operand(r1, RRX)); in TEST()
528 __ And(r10, r1, Operand(r1, RRX)); in TEST()
[all...]
/third_party/node/deps/v8/src/codegen/arm/
H A Dconstants-arm.h233 // RRX is encoded as ROR with shift_imm == 0.
234 // Use a special code to make the distinction. The RRX ShiftOp is only used
237 RRX = -1, enumerator
H A Dassembler-arm.cc372 // RRX as ROR #0 (See below). in Operand()
374 } else if (shift_op == RRX) { in Operand()
383 DCHECK(shift_op != RRX); in Operand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMISelLowering.h102 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
H A DARMExpandPseudoInsts.cpp1395 case ARM::RRX: { in ExpandMI()
H A DARMISelLowering.cpp1581 case ARMISD::RRX: return "ARMISD::RRX"; in getTargetNodeName()
6190 // If we are in thumb mode, we don't have RRX. in Expand64BitShift()
6194 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. in Expand64BitShift()
6205 // The low part is an ARMISD::RRX operand, which shifts the carry in. in Expand64BitShift()
6206 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); in Expand64BitShift()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.cpp158 case OperandARM32::RRX: in encodeShift()

Completed in 110 milliseconds