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Searched refs:RH (Results 1 - 13 of 13) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp506 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
509 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
539 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH); in SplitRes_SELECT()
544 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
547 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
552 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
H A DTargetLowering.cpp5738 SDValue LH, SDValue RL, SDValue RH) const {
5759 // LL, LH, RL, and RH must be either all NULL or all set to a value.
5760 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
5761 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
5827 if (!LH.getNode() && !RH.getNode() &&
5832 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
5833 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
5845 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
[all...]
H A DLegalizeIntegerTypes.cpp2910 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
2912 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_Logical()
2914 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); in ExpandIntRes_Logical()
2923 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
2925 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_MUL()
2929 LL, LH, RL, RH)) in ExpandIntRes_MUL()
2986 DAG.getNode(ISD::MUL, dl, NVT, RH, LL), in ExpandIntRes_MUL()
3070 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
3072 GetExpandedInteger(RHS, RL, RH); in ExpandIntRes_MULFIX()
3078 LL, LH, RL, RH)) { in ExpandIntRes_MULFIX()
[all...]
H A DLegalizeVectorTypes.cpp1677 SDValue LL, LH, RL, RH; in SplitVecRes_SETCC() local
1686 GetSplitVector(N->getOperand(1), RL, RH); in SplitVecRes_SETCC()
1688 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1); in SplitVecRes_SETCC()
1691 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); in SplitVecRes_SETCC()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1699 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
1701 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI);
1754 unsigned B, RegHalf &RH);
1795 // set the information about the found register in RH.
1797 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) {
1864 RH.Reg = Reg;
1865 RH.Sub = Sub;
1866 RH.Low = Low;
1868 if (!HBS::getFinalVRegClass(RH, MR
[all...]
H A DHexagonConstPropagation.cpp1863 bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
2517 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, in evaluateHexRSEQ32() argument
2519 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg)); in evaluateHexRSEQ32()
2521 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH)) in evaluateHexRSEQ32()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
H A DLowerMatrixIntrinsics.cpp743 Value *RH = Builder.CreateExtractElement(Rhs.getColumn(J), K); in LowerMultiply() local
744 Value *Splat = Builder.CreateVectorSplat(BlockSize, RH, "splat"); in LowerMultiply()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp676 SDValue LH, RH; in TryExpandADDWithMul() local
679 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
685 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); in TryExpandADDWithMul()
687 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dconstants-arm64.h877 V(ST, RH, w, 0x40000000), \
881 V(LD, RH, w, 0x40400000), \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4055 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4061 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4070 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4075 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
/third_party/vk-gl-cts/framework/common/
H A DtcuCompressedTexture.cpp775 const deUint8 RH = extend6To8((deUint8)((RH1 << 1) | RH2)); in decompressETC2Block() local
788 const int unclampedR = (x * ((int)RH-(int)RO) + y * ((int)RV-(int)RO) + 4*(int)RO + 2) >> 2; in decompressETC2Block()
/third_party/vixl/src/aarch64/
H A Dconstants-aarch64.h1111 V(ST, RH, w, 0x40000000), \
1115 V(LD, RH, w, 0x40400000), \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3470 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI() local
3476 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH); in lowerSMUL_LOHI()

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