| /third_party/ltp/tools/sparse/sparse-src/validation/ |
| H A D | repeat.h | 10 #define R9(P, S) R6(P,S##0) R6(P,S##1) R6(P,S##2) R6(P,S##3) R6(P,S##4) R6(P,S##5) R6(P,S##6) R6(P,S##7) macro
11 #define R10(P, S) R9(P,S##0) R9(P,S##1)
12 #define R11(P, S) R9(P,S##0) R9(P,S##1) R9(P,S##2) R9(P,S##3)
13 #define R12(P, S) R9(P,S##0) R9(P,S##1) R9(
[all...] |
| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | simple_idct_arm.S | 103 ldr r9, =W3 @ R9=W3
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
159 @@ R5=b2, R6=ROWr16[0], R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
168 ldr r9, =W4 @ R9=W4
189 @@ R5=b2, R6=a0, R7=b3, R8=W2, R9=W4, R10=W6, R11 (free),
201 @@ R9 is free now
202 ldrsh r9, [r14, #12] @ R9=ROWr16[6]
225 @@ R5=b2, R6=a0, R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
236 add r9, r2, r1 @ R9
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.cpp | 43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
|
| /third_party/libunwind/libunwind/src/x86_64/ |
| H A D | init.h | 58 c->dwarf.loc[R9] = REG_INIT_LOC(c, r9, R9); in common_init()
|
| H A D | unwind_i.h | 48 #define R9 9 macro
|
| H A D | Gregs.c | 114 case UNW_X86_64_R9: loc = c->dwarf.loc[R9]; break; in tdep_access_reg()
|
| H A D | Gos-solaris.c | 81 c->dwarf.loc[ R9] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R9, 0); in x86_64_handle_signal_frame()
|
| H A D | Gos-freebsd.c | 120 c->dwarf.loc[ R9] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R9, 0); in x86_64_handle_signal_frame()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 51 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
63 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
|
| H A D | Thumb1FrameLowering.cpp | 211 case ARM::R9: in emitPrologue()
273 case ARM::R9: in emitPrologue()
354 case ARM::R9: in emitPrologue()
877 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
986 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11}; in restoreCalleeSavedRegisters()
|
| /third_party/musl/arch/x32/bits/ |
| H A D | reg.h | 11 #define R9 8 macro
|
| /third_party/musl/arch/x86_64/bits/ |
| H A D | reg.h | 11 #define R9 8 macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| H A D | BPFFrameLowering.cpp | 38 SavedRegs.reset(BPF::R9); in determineCalleeSaves()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 165 {codeview::RegisterId::R9, X86::R9}, in initLLVMToSEHAndCVRegMapping()
645 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
682 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
718 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
754 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
755 return X86::R9; in getX86SubSuperRegisterOrZero()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiBaseInfo.h | 64 case Lanai::R9: in getLanaiRegisterNumbering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86CallingConv.cpp | 86 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
144 // If R9 was already assigned it means that we are after the fourth element in CC_X86_64_VectorCall()
147 if (State.isAllocated(X86::R9)) { in CC_X86_64_VectorCall()
|
| /third_party/rust/crates/libc/src/fuchsia/ |
| H A D | x86_64.rs | 129 pub const R9: ::c_int = 8; consts
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 182 ENTRY(R9) \
200 ENTRY(R9) \
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 215 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
220 XCore::R8, XCore::R9, in getCalleeSavedRegs()
|
| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/ |
| H A D | comc597.mme.h | 440 MME_INSN(0, STATE, R9, IMMED, ZERO, 0x1438/4, NONE, NONE,
507 ADD, ZERO, R9, ZERO, 0, NONE, ALU1),
620 MME_INSN(0, STATE, R9, IMMED, ZERO, 0x1438/4, NONE, NONE,
716 ADD, ZERO, R9, ZERO, 0, NONE, ALU1),
738 MME_INSN(0, ADD, R9, LOAD0, ZERO, 0, NONE, NONE,
742 MME_INSN(0, BLT, ZERO, R9, R8, (2<<14)|0x000e, NONE, NONE,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/ |
| H A D | BPFDisassembler.cpp | 98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 157 Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 115 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 in getCallerSavedRegs()
|