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Searched refs:R5 (Results 1 - 25 of 38) sorted by relevance

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/third_party/skia/third_party/externals/tint/fuzzers/tint_regex_fuzzer/
H A Dregex_fuzzer_tests.cc43 R5 = ";regionregionregionregionregion5;"; in TEST() local
44 std::string all_regions = R1 + R2 + R3 + R4 + R5; in TEST()
51 ASSERT_EQ(R1 + R4 + R3 + R2 + R5, all_regions); in TEST()
59 R5 = ";regionregionregionregionregion5;"; in TEST() local
74 R5 = ";regionregionregionregionregion5;"; in TEST() local
75 std::string all_regions = R1 + R2 + R3 + R4 + R5; in TEST()
77 // this call should swap R4 with R5. in TEST()
80 R5.length(), all_regions); in TEST()
82 ASSERT_EQ(R1 + R2 + R3 + R5 + R4, all_regions); in TEST()
89 R5 in TEST() local
102 R5 = ";regionregionregionregionregion5;"; TEST() local
116 R5 = ";regionregionregionregionregion5;"; TEST() local
128 R5 = ";regionregionregionregionregion5;"; TEST() local
142 R5 = ";regionregionregionregionregion5;"; TEST() local
157 R5 = ";regionregionregionregionregion5;"; TEST() local
172 R5 = "***region5***"; TEST() local
185 R5 = "***region5***"; TEST() local
[all...]
/third_party/ffmpeg/libavcodec/arm/
H A Dsimple_idct_arm.S76 @@ R3=ROWr32[2], R4=ROWr32[3], R5-R11 free
77 orr r5, r4, r3 @ R5=R4 | R3
78 orr r5, r5, r2 @ R5=R4 | R3 | R2
79 orrs r6, r5, r1 @ Test R5 | R1 (the aim is to check if everything is null)
83 orrs r5, r5, r7 @ R5=R4 | R3 | R2 | R7
88 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
107 mul r5, r10, r7 @ R5=W5*ROWr16[1]=b2 (ROWr16[1] must be the second arg, to have the possibility to save 1 cycle)
114 mlane r5, r8, r2, r5 @ R5-=W1*ROWr16[3]=b2 (ROWr16[3] must be the second arg, to have the possibility to save 1 cycle)
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp42 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
47 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
58 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
H A Dcomc597.mme.h153 MME_INSN(0, ADD, R5, LOAD0, ZERO, 0, NONE, NONE,
158 ADD, ZERO, R5, ZERO, 0, NONE, ALU1),
372 STATE, R5, IMMED, ZERO, 0x1438/4, NONE, NONE),
428 MME_INSN(0, ADD, ZERO, R5, ZERO, 0, NONE, ALU0,
464 ADD, R5, LOAD0, ZERO, 0, NONE, NONE),
473 MME_INSN(0, ADD, ZERO, R5, ZERO, 0, NONE, ALU0,
476 ADD, ZERO, R5, ZERO, 0, NONE, ALU1),
523 ADD, R5, LOAD1, ZERO, 0, NONE, NONE),
525 SUB, R5, R5, R
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
/third_party/icu/icu4j/main/classes/core/src/com/ibm/icu/impl/
H A DRow.java36 public static <C0, C1, C2, C3, C4> R5<C0,C1,C2,C3,C4> of(C0 p0, C1 p1, C2 p2, C3 p3, C4 p4) { in of()
37 return new R5<>(p0,p1,p2,p3,p4); in of()
55 public static class R5<C0, C1, C2, C3, C4> extends Row<C0, C1, C2, C3, C4> { class in Row
56 public R5(C0 a, C1 b, C2 c, C3 d, C4 e) { in R5() method in Row.R5
/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/impl/
H A DRow.java40 public static <C0, C1, C2, C3, C4> R5<C0,C1,C2,C3,C4> of(C0 p0, C1 p1, C2 p2, C3 p3, C4 p4) { in of()
41 return new R5<>(p0,p1,p2,p3,p4); in of()
71 public static class R5<C0, C1, C2, C3, C4> extends Row<C0, C1, C2, C3, C4> { class in Row
72 public R5(C0 a, C1 b, C2 c, C3 d, C4 e) { in R5() method in Row.R5
/third_party/skia/third_party/externals/libwebp/src/dsp/
H A Dcommon_sse41.h41 __m128i R0, R1, R2, R3, R4, R5; in VP8PlanarTo24b_SSE41() local
87 const __m128i RG5 = _mm_or_si128(R5, G5); in VP8PlanarTo24b_SSE41()
/third_party/ffmpeg/libswscale/x86/
H A Dyuv_2_rgb.asm197 paddsw m5, m1 ; R1 R3 R5 R7 ...
205 packuswb m0, m3 ; R0 R2 R4 R6 ... R1 R3 R5 R7 ...
212 punpcklbw m6, m_red ; B0 R1 B2 R3 B4 R5 B6 R7 B8 R9 ...
217 punpckhwd m5, m6 ; R4 G4 B4 R5 R6 G6 B6 R7
229 psllq m5, 32 ; -- -- -- -- R4 G4 B4 R5
246 movd [imageq + 12], m5 ; R4 G4 B4 R5
H A Dinput.asm175 pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
185 movd m3, [srcq+14] ; (byte) { R4, B5, G5, R5 }
189 punpckldq m3, m6 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
193 punpcklbw m3, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
199 pmaddwd m3, coeff2 ; (dword) { R4*RY, G5+GY + R5*RY, R6*RY, G7+GY + R7*RY }
274 movd m5, [srcq+14] ; (byte) { R4, B5, G5, R5 }
285 pshufb m5, m4, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
291 punpckldq m5, m3 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
293 punpcklbw m5, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
297 pmaddwd m3, m5, coeffU2 ; (dword) { R4*BU, G5*GU + R5*B
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h54 case Lanai::R5: in getLanaiRegisterNumbering()
/third_party/ffmpeg/libavcodec/x86/
H A Dvp3dsp.asm280 paddsw m5, m6 ; r5 = R5 = F. + B..
308 paddsw m6, OC_8 ; adjust R6 (and R5) for shift
310 paddsw m5, m6 ; r5 = R5 = F. + B..
366 punpckhdq m5, m6 ; r5 = h1 g1 f1 e1 = R5
486 ADD(m6) ; Adjust R6 and R5 before shifting
488 paddsw m5, m6 ; xmm5 = F. + B.. = R5
H A Dsimple_idct.asm87 movq mm3, [blockq + %4] ; R7 R5 r7 r5
176 movq mm3, [blockq + %4] ; R7 R5 r7 r5
253 movq mm3, %4 ; R7 R5 r7 r5
327 movq mm3, %4 ; R7 R5 r7 r5
389 movq mm3, %4 ; R7 R5 r7 r5
444 movq mm3, %4 ; R7 R5 r7 r5
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp220 case ARM::R5: in emitPrologue()
285 case ARM::R5: in emitPrologue()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
875 ARM::R5, ARM::R4, ARM::R3, in spillCalleeSavedRegisters()
985 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
H A DARMBaseRegisterInfo.h48 case R4: case R5: case R6: case R7: in isARMArea1Register()
H A DARMFrameLowering.cpp434 case ARM::R5: in emitPrologue()
641 case ARM::R5: in emitPrologue()
1735 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. in determineCalleeSaves()
1742 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1758 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1945 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
2028 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. in determineCalleeSaves()
2282 // Use R4 and R5 as scratch registers. in adjustForSegmentedStacks()
2283 // We save R4 and R5 before use and restore them before leaving the function. in adjustForSegmentedStacks()
2285 unsigned ScratchReg1 = ARM::R5; in adjustForSegmentedStacks()
[all...]
/third_party/ltp/testcases/kernel/syscalls/ptrace/
H A Dptrace04.c34 R(R0) R(R1) R(R2) R(R3) R(R4) R(R5) R(R6) R(R7)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp214 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
219 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/third_party/ltp/tools/sparse/sparse-src/validation/
H A Drepeat.h6 #define R5(P, S) R3(P,S##0) R3(P,S##1) R3(P,S##2) R3(P,S##3) macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h164 case R4: case R5: case R6: case R7: in isARMLowRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp97 BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp52 Reserved.set(Lanai::R5); in getReservedRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp114 ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 in getCallerSavedRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp86 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,

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