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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.cpp191 PassRegistry *PR = PassRegistry::getPassRegistry(); in LLVMInitializeAMDGPUTarget() local
192 initializeR600ClauseMergePassPass(*PR); in LLVMInitializeAMDGPUTarget()
193 initializeR600ControlFlowFinalizerPass(*PR); in LLVMInitializeAMDGPUTarget()
194 initializeR600PacketizerPass(*PR); in LLVMInitializeAMDGPUTarget()
195 initializeR600ExpandSpecialInstrsPassPass(*PR); in LLVMInitializeAMDGPUTarget()
196 initializeR600VectorRegMergerPass(*PR); in LLVMInitializeAMDGPUTarget()
197 initializeGlobalISel(*PR); in LLVMInitializeAMDGPUTarget()
198 initializeAMDGPUDAGToDAGISelPass(*PR); in LLVMInitializeAMDGPUTarget()
199 initializeGCNDPPCombinePass(*PR); in LLVMInitializeAMDGPUTarget()
200 initializeSILowerI1CopiesPass(*PR); in LLVMInitializeAMDGPUTarget()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetMachine.cpp56 auto &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeWebAssemblyTarget() local
57 initializeWebAssemblyAddMissingPrototypesPass(PR); in LLVMInitializeWebAssemblyTarget()
58 initializeWebAssemblyLowerEmscriptenEHSjLjPass(PR); in LLVMInitializeWebAssemblyTarget()
59 initializeLowerGlobalDtorsPass(PR); in LLVMInitializeWebAssemblyTarget()
60 initializeFixFunctionBitcastsPass(PR); in LLVMInitializeWebAssemblyTarget()
61 initializeOptimizeReturnedPass(PR); in LLVMInitializeWebAssemblyTarget()
62 initializeWebAssemblyArgumentMovePass(PR); in LLVMInitializeWebAssemblyTarget()
63 initializeWebAssemblySetP2AlignOperandsPass(PR); in LLVMInitializeWebAssemblyTarget()
64 initializeWebAssemblyReplacePhysRegsPass(PR); in LLVMInitializeWebAssemblyTarget()
65 initializeWebAssemblyPrepareForLiveIntervalsPass(PR); in LLVMInitializeWebAssemblyTarget()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64TargetMachine.cpp164 auto PR = PassRegistry::getPassRegistry(); in LLVMInitializeAArch64Target() local
165 initializeGlobalISel(*PR); in LLVMInitializeAArch64Target()
166 initializeAArch64A53Fix835769Pass(*PR); in LLVMInitializeAArch64Target()
167 initializeAArch64A57FPLoadBalancingPass(*PR); in LLVMInitializeAArch64Target()
168 initializeAArch64AdvSIMDScalarPass(*PR); in LLVMInitializeAArch64Target()
169 initializeAArch64BranchTargetsPass(*PR); in LLVMInitializeAArch64Target()
170 initializeAArch64CollectLOHPass(*PR); in LLVMInitializeAArch64Target()
171 initializeAArch64CompressJumpTablesPass(*PR); in LLVMInitializeAArch64Target()
172 initializeAArch64ConditionalComparesPass(*PR); in LLVMInitializeAArch64Target()
173 initializeAArch64ConditionOptimizerPass(*PR); in LLVMInitializeAArch64Target()
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H A DAArch64LoadStoreOptimizer.cpp1397 // Checks if any sub- or super-register of PR is callee saved.
1398 auto AnySubOrSuperRegCalleePreserved = [&MF, TRI](MCPhysReg PR) {
1399 return any_of(TRI->sub_and_superregs_inclusive(PR),
1405 // Check if PR or one of its sub- or super-registers can be used for all
1407 auto CanBeUsedForAllClasses = [&RequiredClasses, TRI](MCPhysReg PR) {
1408 return all_of(RequiredClasses, [PR, TRI](const TargetRegisterClass *C) {
1409 return any_of(TRI->sub_and_superregs_inclusive(PR),
1417 for (const MCPhysReg &PR : *RegClass) {
1418 if (DefinedInBB.available(PR) && UsedInBetween.available(PR)
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp103 PassRegistry &PR = *PassRegistry::getPassRegistry(); in LLVMInitializePowerPCTarget() local
105 initializePPCCTRLoopsVerifyPass(PR); in LLVMInitializePowerPCTarget()
107 initializePPCLoopInstrFormPrepPass(PR); in LLVMInitializePowerPCTarget()
108 initializePPCTOCRegDepsPass(PR); in LLVMInitializePowerPCTarget()
109 initializePPCEarlyReturnPass(PR); in LLVMInitializePowerPCTarget()
110 initializePPCVSXCopyPass(PR); in LLVMInitializePowerPCTarget()
111 initializePPCVSXFMAMutatePass(PR); in LLVMInitializePowerPCTarget()
112 initializePPCVSXSwapRemovalPass(PR); in LLVMInitializePowerPCTarget()
113 initializePPCReduceCRLogicalsPass(PR); in LLVMInitializePowerPCTarget()
114 initializePPCBSelPass(PR); in LLVMInitializePowerPCTarget()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86TargetMachine.cpp69 PassRegistry &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeX86Target() local
70 initializeGlobalISel(PR); in LLVMInitializeX86Target()
71 initializeWinEHStatePassPass(PR); in LLVMInitializeX86Target()
72 initializeFixupBWInstPassPass(PR); in LLVMInitializeX86Target()
73 initializeEvexToVexInstPassPass(PR); in LLVMInitializeX86Target()
74 initializeFixupLEAPassPass(PR); in LLVMInitializeX86Target()
75 initializeFPSPass(PR); in LLVMInitializeX86Target()
76 initializeX86CallFrameOptimizationPass(PR); in LLVMInitializeX86Target()
77 initializeX86CmovConverterPassPass(PR); in LLVMInitializeX86Target()
78 initializeX86ExpandPseudoPass(PR); in LLVMInitializeX86Target()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp67 friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR);
76 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
78 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { in operator <<() argument
79 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
260 RegisterSubReg PR = DefI->getOperand(1); in getPredRegFor() local
261 G2P.insert(std::make_pair(Reg, PR)); in getPredRegFor()
262 LLVM_DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); in getPredRegFor()
263 return PR; in getPredRegFor()
327 RegisterSubReg PR = WorkQ.front(); isScalarPred() local
405 RegisterSubReg PR = getPredRegFor(MI->getOperand(1)); convertToPredForm() local
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H A DHexagonTargetMachine.cpp187 PassRegistry &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeHexagonTarget() local
188 initializeHexagonBitSimplifyPass(PR); in LLVMInitializeHexagonTarget()
189 initializeHexagonConstExtendersPass(PR); in LLVMInitializeHexagonTarget()
190 initializeHexagonConstPropagationPass(PR); in LLVMInitializeHexagonTarget()
191 initializeHexagonEarlyIfConversionPass(PR); in LLVMInitializeHexagonTarget()
192 initializeHexagonGenMuxPass(PR); in LLVMInitializeHexagonTarget()
193 initializeHexagonHardwareLoopsPass(PR); in LLVMInitializeHexagonTarget()
194 initializeHexagonLoopIdiomRecognizePass(PR); in LLVMInitializeHexagonTarget()
195 initializeHexagonVectorLoopCarriedReusePass(PR); in LLVMInitializeHexagonTarget()
196 initializeHexagonNewValueJumpPass(PR); in LLVMInitializeHexagonTarget()
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H A DHexagonGenMux.cpp112 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR, in MuxInfo()
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
249 Register PR = PredOp.getReg(); in genMuxInBlock() local
256 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
263 F->second.PredR = PR; in genMuxInBlock()
287 if (!DU.Defs[PR]) in genMuxInBlock()
311 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { in genMuxInBlock()
328 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)); in genMuxInBlock()
H A DHexagonBlockRanges.cpp354 for (unsigned PR = 1, N = TRI.getNumRegs(); PR != N; ++PR) { in computeInitialLiveRanges()
358 if (MCSubRegIterator(PR, &TRI, false).isValid()) in computeInitialLiveRanges()
360 if (Reserved[PR]) in computeInitialLiveRanges()
362 if (BM[PR/32] & (1u << (PR%32))) in computeInitialLiveRanges()
364 RegisterRef R = { PR, 0 }; in computeInitialLiveRanges()
H A DHexagonPeephole.cpp263 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices. in runOnMachineFunction() local
278 Register PSrc = MI.getOperand(PR).getReg(); in runOnMachineFunction()
H A DRDFGraph.h496 PackedRegisterRef PR; // Phi refs store register info directly. member
746 RegisterRef unpack(PackedRegisterRef PR) const { in unpack()
747 return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId)); in unpack()
H A DHexagonBitSimplify.cpp2920 BitTracker::RegisterRef LR, PR; // Loop Register, Preheader Register
2955 PR = P.getOperand(i);
3112 unsigned PR = getDefReg(&I);
3113 if (isConst(PR))
3116 for (auto UI = MRI->use_begin(PR), UE = MRI->use_end(); UI != UE; ++UI) {
3122 if (isBitShuffle(UseI, PR) || isStoreInput(UseI, PR))
3135 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
3274 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp82 PassRegistry &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeNVPTXTarget() local
83 initializeNVVMReflectPass(PR); in LLVMInitializeNVPTXTarget()
84 initializeNVVMIntrRangePass(PR); in LLVMInitializeNVPTXTarget()
85 initializeGenericToNVVMPass(PR); in LLVMInitializeNVPTXTarget()
86 initializeNVPTXAllocaHoistingPass(PR); in LLVMInitializeNVPTXTarget()
87 initializeNVPTXAssignValidGlobalNamesPass(PR); in LLVMInitializeNVPTXTarget()
88 initializeNVPTXLowerArgsPass(PR); in LLVMInitializeNVPTXTarget()
89 initializeNVPTXLowerAllocaPass(PR); in LLVMInitializeNVPTXTarget()
90 initializeNVPTXLowerAggrCopiesPass(PR); in LLVMInitializeNVPTXTarget()
91 initializeNVPTXProxyRegErasurePass(PR); in LLVMInitializeNVPTXTarget()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBPFTargetMachine.cpp36 PassRegistry &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeBPFTarget() local
37 initializeBPFAbstractMemberAccessPass(PR); in LLVMInitializeBPFTarget()
38 initializeBPFMIPeepholePass(PR); in LLVMInitializeBPFTarget()
39 initializeBPFMIPeepholeTruncElimPass(PR); in LLVMInitializeBPFTarget()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
H A DAVRTargetMachine.cpp83 auto &PR = *PassRegistry::getPassRegistry(); in LLVMInitializeAVRTarget() local
84 initializeAVRExpandPseudoPass(PR); in LLVMInitializeAVRTarget()
85 initializeAVRRelaxMemPass(PR); in LLVMInitializeAVRTarget()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp55 PassRegistry *PR = PassRegistry::getPassRegistry(); in LLVMInitializeMipsTarget() local
56 initializeGlobalISel(*PR); in LLVMInitializeMipsTarget()
57 initializeMipsDelaySlotFillerPass(*PR); in LLVMInitializeMipsTarget()
58 initializeMipsBranchExpansionPass(*PR); in LLVMInitializeMipsTarget()
59 initializeMicroMipsSizeReducePass(*PR); in LLVMInitializeMipsTarget()
60 initializeMipsPreLegalizerCombinerPass(*PR); in LLVMInitializeMipsTarget()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/
H A DInstrBuilder.cpp67 const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx); in initializeUsedResources() local
72 << PR.Name << "\n"; in initializeUsedResources()
80 if (PR.BufferSize < 0) { in initializeUsedResources()
84 AnyDispatchHazards |= (PR.BufferSize == 0); in initializeUsedResources()
85 AllInOrderResources &= (PR.BufferSize <= 1); in initializeUsedResources()
90 if (PR.SuperIdx) { in initializeUsedResources()
91 uint64_t Super = ProcResourceMasks[PR.SuperIdx]; in initializeUsedResources()
171 const MCProcResourceDesc &PR = *SM.getProcResource(I); in initializeUsedResources() local
172 if (PR.BufferSize == -1) in initializeUsedResources()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVTargetMachine.cpp38 auto PR = PassRegistry::getPassRegistry(); in LLVMInitializeRISCVTarget() local
39 initializeGlobalISel(*PR); in LLVMInitializeRISCVTarget()
40 initializeRISCVExpandPseudoPass(*PR); in LLVMInitializeRISCVTarget()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/PDB/Native/
H A DNativeTypePointer.h29 codeview::TypeIndex TI, codeview::PointerRecord PR);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DTargetPassConfig.cpp339 const PassRegistry &PR = *PassRegistry::getPassRegistry(); in getPassInfo() local
340 const PassInfo *PI = PR.getPassInfo(PassName); in getPassInfo()
880 const PassRegistry *PR = PassRegistry::getPassRegistry(); in addMachinePasses() local
881 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer")); in addMachinePasses()
/third_party/node/deps/openssl/config/archs/aix64-gcc-as/asm/crypto/
H A Dppccpuid.s2 .csect .text[PR],7
/third_party/node/deps/openssl/config/archs/aix64-gcc-as/asm/crypto/ec/
H A Dx25519-ppc64.s1 .csect .text[PR],7
/third_party/node/deps/openssl/config/archs/aix64-gcc-as/asm_avx2/crypto/
H A Dppccpuid.s2 .csect .text[PR],7
/third_party/node/deps/openssl/config/archs/aix64-gcc-as/asm_avx2/crypto/ec/
H A Dx25519-ppc64.s1 .csect .text[PR],7

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