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Searched refs:PKT3_SET_SH_REG (Results 1 - 11 of 11) sorted by relevance

/third_party/libdrm/tests/amdgpu/
H A Dbasic_tests.c292 #define PKT3_SET_SH_REG 0x76 macro
2300 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); in amdgpu_sync_dependency_test()
2306 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); in amdgpu_sync_dependency_test()
2346 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1); in amdgpu_sync_dependency_test()
2350 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); in amdgpu_sync_dependency_test()
2355 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1); in amdgpu_sync_dependency_test()
2359 ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3); in amdgpu_sync_dependency_test()
2546 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3); in amdgpu_dispatch_init()
2551 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1); in amdgpu_dispatch_init()
2558 ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, in amdgpu_dispatch_init()
[all...]
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h103 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
124 opcode = PKT3_SET_SH_REG; in radeon_set_sh_reg_idx()
H A Dradv_device_generated_commands.c40 /* One PKT3_SET_SH_REG for emitting VBO pointer (32-bit) */ in radv_get_sequence_size()
53 /* One PKT3_SET_SH_REG for emitting push constants pointer (32-bit) */ in radv_get_sequence_size()
58 /* One PKT3_SET_SH_REG writing all inline push constants. */ in radv_get_sequence_size()
255 nir_pkt3(b, PKT3_SET_SH_REG, pkt_cnt), nir_iand_imm(b, vtx_base_sgpr, 0x3FFF), first_vertex, in dgc_emit_userdata_vertex()
559 nir_imm_int(&b, PKT3(PKT3_SET_SH_REG, 1, 0)), load_param16(&b, vbo_reg), in build_dgc_prepare_shader()
653 nir_imm_int(&b, PKT3(PKT3_SET_SH_REG, 1, 0)), in build_dgc_prepare_shader()
668 nir_pkt3(&b, PKT3_SET_SH_REG, inline_len), in build_dgc_prepare_shader()
H A Dradv_private.h1782 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600d_common.h87 #define PKT3_SET_SH_REG 0x76 /* SI and later */ macro
H A Dr600_cs.h171 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
H A Deg_debug.c165 op == PKT3_SET_SH_REG) in ac_parse_packet3()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_pm4.c88 opcode = PKT3_SET_SH_REG; in si_pm4_set_reg()
H A Dsi_build_pm4.h116 radeon_emit(PKT3(PKT3_SET_SH_REG, num, 0)); \
/third_party/mesa3d/src/amd/common/
H A Dsid.h240 #define PKT3_SET_SH_REG 0x76 macro
H A Dac_debug.c276 op == PKT3_SET_UCONFIG_REG_INDEX || op == PKT3_SET_SH_REG || op == PKT3_SET_SH_REG_INDEX) in ac_parse_packet3()
295 case PKT3_SET_SH_REG: in ac_parse_packet3()

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