| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 414 COMPARE_BOTH(Orn(r0, r1, 0), "mvn r0, #0\n"); in TEST()
415 COMPARE_BOTH(Orn(r0, r0, 0xffffffff), ""); in TEST()
421 COMPARE_A32(Orn(r0, r1, 1), in TEST()
430 COMPARE_BOTH(Orn(r0, r1, 0x00ffffff), "orr r0, r1, #0xff000000\n"); in TEST()
431 COMPARE_BOTH(Orn(r0, r1, 0xff00ffff), "orr r0, r1, #0xff0000\n"); in TEST()
439 COMPARE_T32(Orn(r0, r1, 0xabcd2345), in TEST()
448 COMPARE_A32(Orn(r0, r1, r2), in TEST()
452 COMPARE_A32(Orn(r0, r0, r1), in TEST()
456 COMPARE_A32(Orn(r0, r1, r0), in TEST()
460 COMPARE_A32(Orn(r in TEST()
[all...] |
| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 126 M(Orn) \
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| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 126 M(Orn) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 126 M(Orn) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 126 M(Orn) \
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| H A D | test-assembler-aarch32.cc | 3269 __ Orn(r0, r0, 0xffffffff); in TEST()
3313 __ Orn(r4, r0, 0); in TEST()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 556 __ Orn(x2, x0, Operand(x1)); in TEST()
557 __ Orn(w3, w0, Operand(w1, LSL, 4)); in TEST()
558 __ Orn(x4, x0, Operand(x1, LSL, 4)); in TEST()
559 __ Orn(x5, x0, Operand(x1, LSR, 1)); in TEST()
560 __ Orn(w6, w0, Operand(w1, ASR, 1)); in TEST()
561 __ Orn(x7, x0, Operand(x1, ASR, 1)); in TEST()
562 __ Orn(w8, w0, Operand(w1, ROR, 16)); in TEST()
563 __ Orn(x9, x0, Operand(x1, ROR, 16)); in TEST()
564 __ Orn(w10, w0, 0x0000ffff); in TEST()
565 __ Orn(x1 in TEST()
[all...] |
| H A D | test-disasm-aarch64.cc | 2912 COMPARE_MACRO(Orn(w8, w9, 0), "mov w8, #0xffffffff"); in TEST()
2913 COMPARE_MACRO(Orn(x8, x9, 0), "mov x8, #0xffffffffffffffff"); in TEST()
2930 COMPARE_MACRO(Orn(w20, w21, 0xffffffff), "mov w20, w21"); in TEST()
2931 COMPARE_MACRO(Orn(x20, x21, 0xffffffff), "orr x20, x21, #0xffffffff00000000"); in TEST()
2932 COMPARE_MACRO(Orn(x20, x21, 0xffffffffffffffff), "mov x20, x21"); in TEST()
2960 COMPARE_MACRO(Orn(x0, xzr, Operand(w1, SXTW)), in TEST()
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| H A D | test-disasm-neon-aarch64.cc | 1771 COMPARE_MACRO(Orn(v6.V8B(), v7.V8B(), v8.V8B()), "orn v6.8b, v7.8b, v8.8b"); in TEST()
1772 COMPARE_MACRO(Orn(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
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| H A D | test-assembler-neon-aarch64.cc | 6125 __ Orn(v16.V16B(), v0.V16B(), v0.V16B()); // self test in TEST()
6126 __ Orn(v17.V16B(), v0.V16B(), v1.V16B()); // all combinations in TEST()
6127 __ Orn(v24.V8B(), v0.V8B(), v0.V8B()); // self test in TEST()
6128 __ Orn(v25.V8B(), v0.V8B(), v1.V8B()); // all combinations in TEST()
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| H A D | test-assembler-sve-aarch64.cc | 1091 __ Orn(p5.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 391 V(orn, Orn) \
673 inline void Orn(const Register& rd, const Register& rn,
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| H A D | macro-assembler-arm64-inl.h | 64 void TurboAssembler::Orn(const Register& rd, const Register& rn, in Orn() function in v8::internal::TurboAssembler
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | macro-assembler-loong64.h | 400 DEFINE_INSTRUCTION(Orn)
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| H A D | macro-assembler-loong64.cc | 675 void TurboAssembler::Orn(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub() function in v8::internal::TurboAssembler
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 3150 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
3174 void Orn(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
3175 Orn(al, rd, rn, operand); in MacroAssembler()
3177 void Orn(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
3184 Orn(cond, rd, rn, operand); in MacroAssembler()
3190 Orn(cond, rd, rn, operand); in MacroAssembler()
3194 void Orn(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
3198 Orn(flags, al, rd, rn, operand); in MacroAssembler()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1377 __ Orn(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction()
1381 __ Orn(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 796 void Orn(const Register& rd, const Register& rn, const Operand& operand);
2889 V(orn, Orn) \
5598 void Orn(const PRegisterWithLaneSize& pd, in Orn() function in vixl::aarch64::MacroAssembler
5606 void Orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in Orn() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.cc | 846 void MacroAssembler::Orn(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
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