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Searched refs:Order (Results 1 - 25 of 76) sorted by relevance

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/third_party/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/bidi/
H A DTestBidiTransform.java16 import com.ibm.icu.text.BidiTransform.Order;
56 * <code>Bidi.LEVEL_LTR</code> or <code>Bidi.LEVEL_RTL</code>. Order is
57 * always <code>Order.LOGICAL</code> for the input and
58 * <code>Order.VISUAL</code> for the output.
79 String outText = bidiTransform.transform(inText, inLevel, Order.LOGICAL, in autoDirectionTest()
80 outLevel, Order.VISUAL, Mirroring.OFF, 0); in autoDirectionTest()
108 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order.LOGICAL, in allTransformOptionsTest()
113 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order in allTransformOptionsTest()
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/third_party/icu/ohos_icu4j/src/main/tests/ohos/global/icu/dev/test/bidi/
H A DTestBidiTransform.java17 import ohos.global.icu.text.BidiTransform.Order;
59 * <code>Bidi.LEVEL_LTR</code> or <code>Bidi.LEVEL_RTL</code>. Order is
60 * always <code>Order.LOGICAL</code> for the input and
61 * <code>Order.VISUAL</code> for the output.
82 String outText = bidiTransform.transform(inText, inLevel, Order.LOGICAL, in autoDirectionTest()
83 outLevel, Order.VISUAL, Mirroring.OFF, 0); in autoDirectionTest()
111 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order.LOGICAL, in allTransformOptionsTest()
116 { Bidi.LTR, Order.LOGICAL, Bidi.LTR, Order in allTransformOptionsTest()
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/third_party/icu/icu4j/main/classes/core/src/com/ibm/icu/text/
H A DBidiTransform.java18 * <code>{@link Order}</code> indicates the order of text.
56 public enum Order { enum in BidiTransform
176 * Bidi.LTR, Order.VISUAL,
177 * Bidi.RTL, Order.LOGICAL,
186 * Bidi.RTL, Order.LOGICAL,
187 * Bidi.LTR, Order.VISUAL,
199 * <code>{@link Order}</code> values.
204 * <code>{@link Order}</code> values.
222 byte inParaLevel, Order inOrder, in transform()
223 byte outParaLevel, Order outOrde in transform()
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/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/text/
H A DBidiTransform.java19 * <code>{@link Order}</code> indicates the order of text.
57 public enum Order { enum in BidiTransform
167 * Bidi.LTR, Order.VISUAL,
168 * Bidi.RTL, Order.LOGICAL,
177 * Bidi.RTL, Order.LOGICAL,
178 * Bidi.LTR, Order.VISUAL,
190 * <code>{@link Order}</code> values.
195 * <code>{@link Order}</code> values.
212 byte inParaLevel, Order inOrder, in transform()
213 byte outParaLevel, Order outOrde in transform()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h51 unsigned Order; member in llvm::SDDbgValue
61 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(indir) { in SDDbgValue()
70 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(false) { in SDDbgValue()
77 bool IsIndirect, DebugLoc DL, unsigned Order, in SDDbgValue()
79 : Var(Var), Expr(Expr), DL(DL), Order(Order), IsIndirect(IsIndirect) { in SDDbgValue()
121 unsigned getOrder() const { return Order; } in getOrder()
147 unsigned Order; member in llvm::SDDbgLabel
151 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel()
161 unsigned getOrder() const { return Order; } in getOrder()
76 SDDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VRegOrFrameIdx, bool IsIndirect, DebugLoc DL, unsigned Order, enum DbgValueKind Kind) SDDbgValue() argument
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H A DScheduleDAGSDNodes.cpp734 DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
746 if (!Order || DVOrder == Order) {
764 unsigned Order = N->getIROrder();
765 if (!Order || Seen.count(Order)) {
772 // If a new instruction was generated for this Order number, record it.
777 Seen.insert(Order);
778 Orders.push_back({Order, NewInsn});
783 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
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/third_party/vk-gl-cts/framework/referencerenderer/
H A DrrVertexAttrib.cpp59 template<typename SrcScalarType, typename DstScalarType, typename Order>
65 dst[Order::T0] = DstScalarType(aligned[0]); in readOrder()
66 if (size >= 2) dst[Order::T1] = DstScalarType(aligned[1]); in readOrder()
67 if (size >= 3) dst[Order::T2] = DstScalarType(aligned[2]); in readOrder()
68 if (size >= 4) dst[Order::T3] = DstScalarType(aligned[3]); in readOrder()
71 template<typename SrcScalarType, typename Order>
79 dst[Order::T0] = float(aligned[0]) / float(range); in readUnormOrder()
80 if (size >= 2) dst[Order::T1] = float(aligned[1]) / float(range); in readUnormOrder()
81 if (size >= 3) dst[Order::T2] = float(aligned[2]) / float(range); in readUnormOrder()
82 if (size >= 4) dst[Order in readUnormOrder()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/
H A DDynamicLibrary.cpp76 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument
77 if (Order & SO_LoadOrder) { in LibLookup()
91 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument
92 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup()
95 if (!Process || (Order & SO_LoadedFirst)) { in Lookup()
96 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
105 if (Order & SO_LoadedLast) { in Lookup()
106 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DAllocationOrder.h1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
31 ArrayRef<MCPhysReg> Order; member in llvm::AllocationOrder
49 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
60 Limit = Order.size(); in next()
62 unsigned Reg = Order[Pos++]; in next()
79 return Order[Pos++]; in nextWithDups()
H A DRegAllocGreedy.cpp455 const AllocationOrder &Order);
458 const AllocationOrder &Order);
460 const AllocationOrder &Order,
472 unsigned getCheapestEvicteeWeight(const AllocationOrder &Order,
492 AllocationOrder &Order,
502 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
763 AllocationOrder &Order, in tryAssign()
766 Order.rewind(); in tryAssign()
768 while ((PhysReg = Order.next())) in tryAssign()
771 if (!PhysReg || Order in tryAssign()
762 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, const SmallVirtRegSet &FixedRegisters) tryAssign() argument
1022 getCheapestEvicteeWeight(const AllocationOrder &Order, LiveInterval &VirtReg, SlotIndex Start, SlotIndex End, float *BestEvictweight) getCheapestEvicteeWeight() argument
1106 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) tryEvict() argument
1483 splitCanCauseEvictionChain(unsigned Evictee, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) splitCanCauseEvictionChain() argument
1543 splitCanCauseLocalSpill(unsigned VirtRegToSplit, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) splitCanCauseLocalSpill() argument
1583 calcGlobalSplitCost(GlobalSplitCandidate &Cand, const AllocationOrder &Order, bool *CanCauseEvictionChain) calcGlobalSplitCost() argument
1829 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) tryRegionSplit() argument
1872 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR, bool *CanCauseEvictionChain) calculateRegionSplitCost() argument
2019 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) tryBlockSplit() argument
2086 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) tryInstructionSplit() argument
2229 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) tryLocalSplit() argument
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H A DRegisterClassInfo.cpp98 if (!RCI.Order) in compute()
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
138 RCI.Order[N++] = PhysReg; in compute()
158 dbgs() << ' ' << printReg(RCI.Order[I], TRI); in compute()
H A DAllocationOrder.cpp1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
37 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) in AllocationOrder()
51 assert(is_contained(Order, Hints[I]) && in AllocationOrder()
H A DLocalStackSlotAllocation.cpp56 // Order reference instruction appears in program. Used to ensure
59 unsigned Order; member in __anon24034::FrameRef
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
66 return std::tie(LocalOffset, FrameIdx, Order) < in operator <()
67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); in operator <()
302 unsigned Order = 0; in insertFrameReferenceRegisters() local
330 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++)); in insertFrameReferenceRegisters()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceIntrinsics.cpp32 bool Intrinsics::isMemoryOrderValid(IntrinsicID ID, uint64_t Order, in isMemoryOrderValid() argument
51 if (OrderOther > Order) in isMemoryOrderValid()
53 if (Order == MemoryOrderRelease && OrderOther != MemoryOrderRelaxed) in isMemoryOrderValid()
60 switch (Order) { in isMemoryOrderValid()
68 switch (Order) { in isMemoryOrderValid()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h750 void setIROrder(unsigned Order) { IROrder = Order; } in setIROrder() argument
1096 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1098 IROrder(Order), debugLoc(std::move(dl)) {
1127 SDLoc(const Instruction *I, int Order) : IROrder(Order) { in SDLoc() argument
1128 assert(Order >= 0 && "bad IROrder"); in SDLoc()
1274 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1296 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1428 AtomicSDNode(unsigned Opc, unsigned Order, cons argument
1482 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) MemIntrinsicSDNode() argument
1514 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M) ShuffleVectorSDNode() argument
1765 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, int64_t Size, int64_t Offset) LifetimeSDNode() argument
2102 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L) LabelSDNode() argument
2192 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) LSBaseSDNode() argument
2226 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) LoadSDNode() argument
2254 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) StoreSDNode() argument
2286 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) MaskedLoadStoreSDNode() argument
2331 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, bool IsExpanding, EVT MemVT, MachineMemOperand *MMO) MaskedLoadSDNode() argument
2360 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing, EVT MemVT, MachineMemOperand *MMO) MaskedStoreSDNode() argument
2396 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) MaskedGatherScatterSDNode() argument
2438 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) MaskedGatherSDNode() argument
2457 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) MaskedScatterSDNode() argument
2481 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs) MachineSDNode() argument
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H A DScheduleDAG.h56 Order ///< Any other ordering dependency. enumerator
89 /// Additional information about Order dependencies.
124 : Dep(S, Order), Contents(), Latency(0) { in SDep()
165 /// Tests if this is an Order dependence between two memory accesses
169 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory()
173 /// Tests if this is an Order dependence that is marked as a barrier.
175 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier()
183 /// Tests if this is an Order dependence that is marked as
187 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias()
195 return getKind() == Order in isWeak()
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/third_party/lzma/CPP/7zip/Compress/
H A DPpmdEncoder.cpp38 if (Order == -1) Order = kOrders[(unsigned)level]; in Normalize()
118 props.Order = (Byte)v; in SetCoderProperties()
134 props[0] = (Byte)_props.Order; in WriteCoderProperties()
157 Ppmd7_Init(&_ppmd, (unsigned)_props.Order); in Code()
H A DPpmdEncoder.h21 int Order; member
27 Order = -1; in CEncProps()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp197 SmallVector<RegionNode *, 8> Order; member in __anon25201::StructurizeCFG
353 if (is_contained(Order, *I)) in orderNodes()
365 Order.push_back(*LoopI); in orderNodes()
375 Order.push_back(*I); in orderNodes()
382 std::reverse(Order.begin(), Order.end()); in orderNodes()
520 for (RegionNode *RN : reverse(Order)) { in collectInfos()
726 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : in getNextFlow()
727 Order.back()->getEntry(); in getNextFlow()
757 if (!Order in needPostfix()
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/third_party/icu/icu4c/source/test/intltest/
H A Dtscoll.cpp392 LocalArray<Order> orders(getOrders(iter, orderLength)); in backAndForth()
485 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &orderLength) in getOrders()
489 LocalArray<Order> orders(new Order[maxSize]); in getOrders()
499 Order *temp = new Order[maxSize]; in getOrders()
501 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order)); in getOrders()
518 Order *temp = new Order[size]; in getOrders()
520 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order)); in getOrders()
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H A Ditercoll.cpp191 Order *orders = getOrders(*iter, orderLength); in TestOffset()
230 Order *order = getOrders(*iter, orderLength); in TestOffset()
233 Order *order2 = getOrders(*iter, order2Length); in TestOffset()
234 if (orderLength != order2Length || uprv_memcmp(order, order2, orderLength * sizeof(Order)) != 0) { in TestOffset()
246 if (orderLength != order2Length || uprv_memcmp(order, order2, orderLength * sizeof(Order)) != 0) { in TestOffset()
258 if (orderLength != order2Length || uprv_memcmp(order, order2, orderLength * sizeof(Order)) != 0) { in TestOffset()
270 if (orderLength != order2Length || uprv_memcmp(order, order2, orderLength * sizeof(Order)) != 0) { in TestOffset()
H A Dssearch.cpp334 struct Order struct
350 const Order *get(int32_t index) const;
359 Order *list;
367 list = new Order[listMax]; in OrderList()
390 list = new Order[listMax]; in OrderList()
421 Order *newList = new Order[listMax]; in add()
423 uprv_memcpy(newList, list, listSize * sizeof(Order)); in add()
435 const Order *OrderList::get(int32_t index) const in get()
446 const Order *orde in getLowOffset()
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H A Dtscoll.h28 struct Order struct in IntlTestCollator
53 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86ISelLowering.h1543 X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, in X86StoreSDNode() argument
1546 :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {} in X86StoreSDNode()
1561 X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, in X86MaskedStoreSDNode() argument
1564 : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {} in X86MaskedStoreSDNode()
1579 TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, in TruncSStoreSDNode() argument
1581 : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {} in TruncSStoreSDNode()
1591 TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, in TruncUSStoreSDNode() argument
1593 : X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {} in TruncUSStoreSDNode()
1603 MaskedTruncSStoreSDNode(unsigned Order, in MaskedTruncSStoreSDNode() argument
1606 : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, d in MaskedTruncSStoreSDNode()
1616 MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) MaskedTruncUSStoreSDNode() argument
1631 X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) X86MaskedGatherScatterSDNode() argument
1649 X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) X86MaskedGatherSDNode() argument
1663 X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) X86MaskedScatterSDNode() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp59 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument
66 for (MCPhysReg Reg : Order) in addHints()
70 for (MCPhysReg Reg : Order) in addHints()
78 ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
88 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
131 for (MCPhysReg OrderReg : Order) in getRegAllocationHints()
161 addHints(Order, Hints, RC, MRI); in getRegAllocationHints()
182 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI); in getRegAllocationHints()
77 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const getRegAllocationHints() argument

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