Searched refs:Neon8 (Results 1 - 6 of 6) sorted by relevance
| /third_party/node/deps/v8/src/execution/arm/ |
| H A D | simulator-arm.cc | 3423 size = Neon8; in DecodeTypeVFP()
3429 case Neon8: { in DecodeTypeVFP()
4412 DCHECK_EQ(Neon8, size); in DecodeAdvancedSIMDTwoOrThreeRegisters()
4432 case Neon8: { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4467 case Neon8: { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4492 case Neon8: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4514 case Neon8: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4576 case Neon8: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4595 case Neon8: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4622 case Neon8 in DecodeAdvancedSIMDTwoOrThreeRegisters()
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 1635 __ vld1(Neon8, NeonListOperand(i.OutputDoubleRegister()), in AssembleArchInstruction()
1640 __ vst1(Neon8, NeonListOperand(i.InputDoubleRegister(0)), in AssembleArchInstruction()
1645 __ vld1(Neon8, NeonListOperand(i.OutputSimd128Register()), in AssembleArchInstruction()
1650 __ vst1(Neon8, NeonListOperand(i.InputSimd128Register(0)), in AssembleArchInstruction()
1774 __ vld1(Neon8, NeonListOperand(i.OutputSimd128Register()), in AssembleArchInstruction()
2691 __ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0)); in AssembleArchInstruction()
2710 __ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
2714 ASSEMBLE_SIMD_SHIFT_LEFT(vshl, 3, Neon8, NeonS8); in AssembleArchInstruction()
2718 ASSEMBLE_SIMD_SHIFT_RIGHT(vshr, 3, Neon8, NeonS8); in AssembleArchInstruction()
2725 __ vadd(Neon8, in AssembleArchInstruction()
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| H A D | instruction-selector-arm.cc | 3037 g.UseImmediate(Neon8), g.UseImmediate(index % 16)); in VisitI8x16Shuffle()
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| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 332 assm->vst1(Neon8, NeonListOperand(src.low_fp(), 2), NeonMemOperand(addr)); in Store()
366 assm->vld1(Neon8, NeonListOperand(dst.low_fp(), 2), NeonMemOperand(addr)); in Load()
669 __ vld1(Neon8, NeonListOperand(dst.low_fp(), 2), in LoadInternal()
824 vst1(Neon8, NeonListOperand(src.low_fp(), 2), in Store()
2358 vld1(Neon8, NeonListOperand(dst.low_fp()), in LoadTransform()
2362 vld1(Neon8, NeonListOperand(dst.low_fp()), in LoadTransform()
2397 vld1r(Neon8, NeonListOperand(liftoff::GetSimd128Register(dst)), in LoadTransform()
3507 vdup(Neon8, liftoff::GetSimd128Register(dst), src.gp());
3533 vneg(Neon8, liftoff::GetSimd128Register(dst),
3575 vzip(Neon8, mas
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| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | constants-arm.h | 296 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 }; enumerator
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| H A D | assembler-arm.cc | 3928 case Neon8: in vdup()
4076 DCHECK_EQ(Neon8, size); // size == 0 for vmvn in EncodeNeonUnaryOp()
4080 DCHECK_EQ(Neon8, size); // size == 0 for vswp in EncodeNeonUnaryOp()
4172 emit(EncodeNeonUnaryOp(VMVN, NEON_Q, Neon8, dst.code(), src.code())); in vmvn()
4180 emit(EncodeNeonUnaryOp(VSWP, NEON_D, Neon8, dst.code(), src.code())); in vswp()
4187 emit(EncodeNeonUnaryOp(VSWP, NEON_Q, Neon8, dst.code(), src.code())); in vswp()
5065 emit(EncodeNeonUnaryOp(VCNT, NEON_Q, Neon8, dst.code(), src.code())); in vcnt()
5519 *this = LoadStoreLaneParams(laneidx, Neon8, 8); in LoadStoreLaneParams()
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