Home
last modified time | relevance | path

Searched refs:Neon64 (Results 1 - 6 of 6) sorted by relevance

/third_party/node/deps/v8/src/codegen/arm/
H A Dconstants-arm.h296 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 }; enumerator
315 DCHECK_NE(Neon64, size); in NeonSizeToDataType()
H A Dmacro-assembler-arm.cc1018 vsli(Neon64, dst_d_reg, src_d_reg, 32); in CallRecordWriteStub()
1024 vsri(Neon64, dst_d_reg, src_d_reg, 32); in CallRecordWriteStub()
1148 if (sz == Neon64) { in CallRecordWriteStub()
1149 // vld1s is not valid for Neon64. in CallRecordWriteStub()
1150 vld1(Neon64, dst_list, src); in CallRecordWriteStub()
1158 if (sz == Neon64) { in CallRecordWriteStub()
1159 // vst1s is not valid for Neon64. in CallRecordWriteStub()
1160 vst1(Neon64, src_list, dst); in CallRecordWriteStub()
2736 vsub(Neon64, dst, dst, tmp); in CallRecordWriteStub()
H A Dassembler-arm.cc3960 DCHECK_NE(Neon64, size); in EncodeNeonDupOp()
5525 *this = LoadStoreLaneParams(laneidx, Neon64, 1); in LoadStoreLaneParams()
/third_party/node/deps/v8/src/execution/arm/
H A Dsimulator-arm.cc4409 static_cast<NeonSize>(static_cast<int>(Neon64) - instr->Bits(8, 7)); in DecodeAdvancedSIMDTwoOrThreeRegisters()
4447 case Neon64: { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4504 case Neon64: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4529 case Neon64: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4587 case Neon64: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4604 case Neon64: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4807 case Neon64: in DecodeAdvancedSIMDTwoOrThreeRegisters()
5006 case Neon64: { in DecodeAdvancedSIMDTwoOrThreeRegisters()
5025 case Neon64: { in DecodeAdvancedSIMDTwoOrThreeRegisters()
5125 case Neon64 in DecodeAdvancedSIMDDataProcessing()
[all...]
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h657 __ vld1(Neon64, NeonListOperand(dst.fp()), in LoadInternal()
818 vst1(Neon64, NeonListOperand(src.fp()), NeonMemOperand(actual_dst_addr)); in Store()
2391 vld1(Neon64, NeonListOperand(dest.low()), in LoadTransform()
2862 vsub(Neon64, liftoff::GetSimd128Register(dst), zero, in emit_i64x2_neg()
2908 vadd(Neon64, liftoff::GetSimd128Register(dst), in emit_i64x2_add()
2914 vsub(Neon64, liftoff::GetSimd128Register(dst), in emit_i64x2_sub()
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc2059 __ vadd(Neon64, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2064 __ vsub(Neon64, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2121 __ vsub(Neon64, dst, dst, i.InputSimd128Register(0)); in AssembleArchInstruction()
3295 __ vld1(Neon64, NeonListOperand(dst.low()), i.NeonInputOperand(0)); in AssembleArchInstruction()

Completed in 36 milliseconds