| /third_party/node/deps/v8/src/execution/arm/ |
| H A D | simulator-arm.cc | 3419 NeonSize size = Neon32; in DecodeTypeVFP()
3446 case Neon32: { in DecodeTypeVFP()
4421 case Neon32: { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4449 case Neon32: { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4500 case Neon32: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4524 case Neon32: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4583 case Neon32: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4601 case Neon32: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4628 case Neon32: in DecodeAdvancedSIMDTwoOrThreeRegisters()
4656 case Neon32 in DecodeAdvancedSIMDTwoOrThreeRegisters()
[all...] |
| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 2046 __ vdup(Neon32, dst, i.InputRegister(0)); in AssembleArchInstruction()
2098 __ vtrn(Neon32, tmp1.low(), tmp1.high()); in AssembleArchInstruction()
2100 __ vtrn(Neon32, tmp2.low(), tmp2.high()); in AssembleArchInstruction()
2125 ASSEMBLE_SIMD_SHIFT_LEFT(vshl, 6, Neon32, NeonS64); in AssembleArchInstruction()
2130 // Neon32 as the size. in AssembleArchInstruction()
2131 ASSEMBLE_SIMD_SHIFT_RIGHT(vshr, 6, Neon32, NeonS64); in AssembleArchInstruction()
2136 // Neon32 as the size. in AssembleArchInstruction()
2137 ASSEMBLE_SIMD_SHIFT_RIGHT(vshr, 6, Neon32, NeonU64); in AssembleArchInstruction()
2166 __ vdup(Neon32, i.OutputSimd128Register(), in AssembleArchInstruction()
2314 __ vdup(Neon32, in AssembleArchInstruction()
[all...] |
| H A D | instruction-selector-arm.cc | 3015 g.UseImmediate(Neon32), g.UseImmediate(index % 4)); in VisitI8x16Shuffle()
|
| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 2374 vld1(Neon32, NeonListOperand(dst.low_fp()), in LoadTransform()
2378 vld1(Neon32, NeonListOperand(dst.low_fp()), in LoadTransform()
2386 vld1s(Neon32, NeonListOperand(dst.low_fp()), 0, in LoadTransform()
2403 vld1r(Neon32, NeonListOperand(liftoff::GetSimd128Register(dst)), in LoadTransform()
2406 vld1(Neon32, NeonListOperand(dst.low_fp()), in LoadTransform()
2649 vdup(Neon32, liftoff::GetSimd128Register(dst), src.fp(), 0); in emit_f32x4_splat()
2831 vdup(Neon32, dst_simd, src.low_gp()); in emit_i64x2_splat()
2873 liftoff::EmitSimdShift<liftoff::kLeft, NeonS64, Neon32>(this, dst, lhs, rhs); in emit_i64x2_shl()
2885 liftoff::EmitSimdShift<liftoff::kRight, NeonS64, Neon32>(this, dst, lhs, rhs); in emit_i64x2_shr_s()
2897 liftoff::EmitSimdShift<liftoff::kRight, NeonU64, Neon32>(thi in emit_i64x2_shr_u()
[all...] |
| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | macro-assembler-arm.cc | 1009 vdup(Neon32, scratch, src_d_reg, src_offset); in CallRecordWriteStub()
1016 vdup(Neon32, dst_d_reg, src_d_reg, 0); in CallRecordWriteStub()
1022 vdup(Neon32, dst_d_reg, src_d_reg, 1); in CallRecordWriteStub()
2676 vceq(Neon32, dst, src1, src2); in CallRecordWriteStub()
2677 vrev64(Neon32, scratch, dst); in CallRecordWriteStub()
2685 vceq(Neon32, dst, src1, src2); in CallRecordWriteStub()
2686 vrev64(Neon32, tmp, dst); in CallRecordWriteStub()
2714 vceq(Neon32, tmp, tmp, 0); in CallRecordWriteStub()
|
| H A D | constants-arm.h | 296 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 }; enumerator
|
| H A D | assembler-arm.cc | 3912 int u = NeonDataTypeToSize(dt) == Neon32 ? 0 : NeonU(dt); in vmov()
3934 case Neon32: in vdup()
4087 DCHECK_EQ(Neon32, size); in EncodeNeonUnaryOp()
4094 DCHECK_EQ(Neon32, size); in EncodeNeonUnaryOp()
4194 emit(EncodeNeonUnaryOp(VABSF, NEON_Q, Neon32, dst.code(), src.code())); in vabs()
4208 emit(EncodeNeonUnaryOp(VNEGF, NEON_Q, Neon32, dst.code(), src.code())); in vneg()
4740 emit(EncodeNeonUnaryOp(VRECPE, NEON_Q, Neon32, dst.code(), src.code())); in vrecpe()
4747 emit(EncodeNeonUnaryOp(VRSQRTE, NEON_Q, Neon32, dst.code(), src.code())); in vrsqrte()
4968 if (size == Neon32) { // vzip.32 Dd, Dm is a pseudo-op for vtrn.32 Dd, Dm. in vzip()
4986 if (size == Neon32) { // vuz in vuzp()
[all...] |